linux-kernel - Re: [PATCH V3 04/11] CRIS v32: nand: set ECC algorithm explicitly

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Thu, 21 Apr 2016 22:18:11 +0200
From:	Boris Brezillon <boris.brezillon@...e-electrons.com>
To:	Rafał Miłecki <zajec5@...il.com>
Cc:	linux-mtd@...ts.infradead.org, Mikael Starvik <starvik@...s.com>,
	Jesper Nilsson <jesper.nilsson@...s.com>,
	Brian Norris <computersforpeace@...il.com>,
	linux-cris-kernel@...s.com (open list:CRIS PORT),
	linux-kernel@...r.kernel.org (open list)
Subject: Re: [PATCH V3 04/11] CRIS v32: nand: set ECC algorithm explicitly

On Sun, 17 Apr 2016 22:53:00 +0200
Rafał Miłecki <zajec5@...il.com> wrote:

> This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
> enum nand_ecc_algo).
> 
> Signed-off-by: Rafał Miłecki <zajec5@...il.com>

Mikael, Jesper, could you review/ack this patch? I'd like to take it
into the nand tree to avoid any dependency problems.

Thanks,

Boris

> ---
>  arch/cris/arch-v32/drivers/mach-a3/nandflash.c | 1 +
>  arch/cris/arch-v32/drivers/mach-fs/nandflash.c | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
> index 5aa3f51..3f646c7 100644
> --- a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
> +++ b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
> @@ -157,6 +157,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void)
>  	/* 20 us command delay time */
>  	this->chip_delay = 20;
>  	this->ecc.mode = NAND_ECC_SOFT;
> +	this->ecc.algo = NAND_ECC_HAMMING;
>  
>  	/* Enable the following for a flash based bad block table */
>  	/* this->bbt_options = NAND_BBT_USE_FLASH; */
> diff --git a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
> index a7c17b0..a745405 100644
> --- a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
> +++ b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
> @@ -148,6 +148,7 @@ struct mtd_info *__init crisv32_nand_flash_probe(void)
>  	/* 20 us command delay time */
>  	this->chip_delay = 20;
>  	this->ecc.mode = NAND_ECC_SOFT;
> +	this->ecc.algo = NAND_ECC_HAMMING;
>  
>  	/* Enable the following for a flash based bad block table */
>  	/* this->bbt_options = NAND_BBT_USE_FLASH; */



-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com