linux-kernel - RE: [v8, 1/7] Documentation: DT: update Freescale DCFG compatible

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Date:	Tue, 26 Apr 2016 02:43:10 +0000
From:	Yangbo Lu <yangbo.lu@....com>
To:	Mark Rutland <mark.rutland@....com>
CC:	"linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
	"linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
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	"iommu@...ts.linux-foundation.org" <iommu@...ts.linux-foundation.org>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"ulf.hansson@...aro.org" <ulf.hansson@...aro.org>,
	Scott Wood <scott.wood@....com>,
	Rob Herring <robh+dt@...nel.org>,
	"Russell King" <linux@....linux.org.uk>,
	Jochen Friedrich <jochen@...am.de>,
	"Joerg Roedel" <joro@...tes.org>,
	Claudiu Manoil <claudiu.manoil@...escale.com>,
	Bhupesh Sharma <bhupesh.sharma@...escale.com>,
	Zhao Qiang <qiang.zhao@...escale.com>,
	Kumar Gala <galak@...eaurora.org>,
	"Santosh Shilimkar" <ssantosh@...nel.org>,
	Yang-Leo Li <leoyang.li@....com>,
	Xiaobo Xie <xiaobo.xie@....com>
Subject: RE: [v8, 1/7] Documentation: DT: update Freescale DCFG compatible

Hi Mark,


> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland@....com]
> Sent: Friday, April 22, 2016 9:12 PM
> To: Yangbo Lu
> Cc: linux-mmc@...r.kernel.org; linuxppc-dev@...ts.ozlabs.org;
> devicetree@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linux-
> kernel@...r.kernel.org; linux-clk@...r.kernel.org; linux-
> i2c@...r.kernel.org; iommu@...ts.linux-foundation.org;
> netdev@...r.kernel.org; ulf.hansson@...aro.org; Scott Wood; Rob Herring;
> Russell King; Jochen Friedrich; Joerg Roedel; Claudiu Manoil; Bhupesh
> Sharma; Zhao Qiang; Kumar Gala; Santosh Shilimkar; Yang-Leo Li; Xiaobo
> Xie
> Subject: Re: [v8, 1/7] Documentation: DT: update Freescale DCFG
> compatible
> 
> On Fri, Apr 22, 2016 at 02:27:38PM +0800, Yangbo Lu wrote:
> > Update Freescale DCFG compatible with 'fsl,<chip>-dcfg' instead of
> > 'fsl,ls1021a-dcfg' to include more chips.
> >
> > Signed-off-by: Yangbo Lu <yangbo.lu@....com>
> > ---
> > Changes for v8:
> > 	- Added this patch
> > ---
> >  Documentation/devicetree/bindings/arm/fsl.txt | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/fsl.txt
> > b/Documentation/devicetree/bindings/arm/fsl.txt
> > index 752a685..1d5f512 100644
> > --- a/Documentation/devicetree/bindings/arm/fsl.txt
> > +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> > @@ -119,7 +119,7 @@ Freescale DCFG
> >  configuration and status for the device. Such as setting the
> > secondary  core start address and release the secondary core from
> holdoff and startup.
> >    Required properties:
> > -  - compatible: should be "fsl,ls1021a-dcfg"
> > +  - compatible: should be "fsl,<chip>-dcfg"
> 
> Please list specific values expected for <chip>, while jusy saying <chip>
> may be more generic, it makes it practically impossible to search for the
> correct binding given a compatible string, and it's vague as to exaclty
> what <chip> should be.

[Lu Yangbo-B47093] Thanks for your comment. I will list the possible chips.

> 
> Thanks,
> Mark.
> 
> 
> 
> >    - reg : should contain base address and length of DCFG
> > memory-mapped registers
> >
> >  Example:
> > --
> > 2.1.0.27.g96db324
> >
> > --
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> >