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Date:	Fri, 6 May 2016 12:43:07 +0000
From:	"Chen, Yu C" <yu.c.chen@...el.com>
To:	Thomas Gleixner <tglx@...utronix.de>
CC:	"x86@...nel.org" <x86@...nel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>, "Gao, Bin" <bin.gao@...el.com>,
	Len Brown <lenb@...nel.org>,
	"Rafael J. Wysocki" <rafael@...nel.org>,
	"3 . 14+ # 3 . 14+" <stable@...r.kernel.org>
Subject: RE: [PATCH] x86, tsc: Fix tsc ratio calibration to avoid broken
 mdelay



> -----Original Message-----
> From: Thomas Gleixner [mailto:tglx@...utronix.de]
> Sent: Friday, May 06, 2016 5:53 PM
> To: Chen, Yu C
> Cc: x86@...nel.org; linux-kernel@...r.kernel.org; Ingo Molnar; H. Peter Anvin;
> Gao, Bin; Len Brown; Rafael J. Wysocki; 3 . 14+ # 3 . 14+
> Subject: Re: [PATCH] x86, tsc: Fix tsc ratio calibration to avoid broken mdelay
> 
> 
> On Fri, 6 May 2016, Thomas Gleixner wrote:
> > On Fri, 6 May 2016, yu.c.chen@...el.com wrote:
> > > From: Chen Yu <yu.c.chen@...el.com>
> > >
> > > Currently we fetch the tsc radio by:
> > > ratio = (lo >> 8) & 0x1f;
> > > thus get bit8~bit12 of the MSR_PLATFORM_INFO, however according to
> > > Intel 64 and IA-32 Architectures Software Developer Manual 35.5, the
> > > ratio bit should be bit8~bit15, otherwise we might get incorrect tsc
> > > ratio and cause system hang later(mdelay corrupted).
> >
> > The resulting issue is that both TSC frequency, which is used for
> > udelay, and the lapic timer frequency are wrong. mdelay is just the
> > visible damage caused by that.
> 
> Aside of that:
> 
> > Cc: 3.14+ <stable@...r.kernel.org> # 3.14+
> 
> Please use:
> 
> Fixes: commit '....'
> 
> next time, which identifies the kernel version to which this needs to be
> backported and gives a reference to the commit which caused the issue.
> 
OK, thanks!

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