linux-kernel - Re: [PATCH 00/12] TLB/XPA fixes & cleanups

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Date:	Tue, 10 May 2016 14:44:26 +0200
From:	Ralf Baechle <ralf@...ux-mips.org>
To:	Paul Burton <paul.burton@...tec.com>
Cc:	linux-mips@...ux-mips.org, James Hogan <james.hogan@...tec.com>,
	Adam Buchbinder <adam.buchbinder@...il.com>,
	"Maciej W. Rozycki" <macro@...tec.com>,
	Joshua Kinard <kumba@...too.org>,
	Huacai Chen <chenhc@...ote.com>,
	"Maciej W. Rozycki" <macro@...ux-mips.org>,
	Paul Gortmaker <paul.gortmaker@...driver.com>,
	"Aneesh Kumar K.V" <aneesh.kumar@...ux.vnet.ibm.com>,
	linux-kernel@...r.kernel.org,
	"Peter Zijlstra (Intel)" <peterz@...radead.org>,
	David Hildenbrand <dahi@...ux.vnet.ibm.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	David Daney <david.daney@...ium.com>,
	Jonas Gorski <jogo@...nwrt.org>,
	Markos Chandras <markos.chandras@...tec.com>,
	Ingo Molnar <mingo@...nel.org>,
	Alex Smith <alex.smith@...tec.com>,
	"Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
	Florian Fainelli <f.fainelli@...il.com>
Subject: Re: [PATCH 00/12] TLB/XPA fixes & cleanups

On Fri, Apr 15, 2016 at 11:36:48AM +0100, Paul Burton wrote:

> This series fixes up a number of issues introduced by commit
> c5b367835cfc ("MIPS: Add support for XPA."), including breakage of the
> MIPS32 with 36 bit physical addressing case & clobbering of $1 upon TLB
> refill exceptions. Along the way a number of cleanups are made, which
> leaves pgtable-bits.h in particular much more readable than before.
> 
> The series applies atop v4.6-rc3.
> 
> James Hogan (4):
>   MIPS: Separate XPA CPU feature into LPA and MVH
>   MIPS: Fix HTW config on XPA kernel without LPA enabled
>   MIPS: mm: Don't clobber $1 on XPA TLB refill
>   MIPS: mm: Don't do MTHC0 if XPA not present
> 
> Paul Burton (8):
>   MIPS: Remove redundant asm/pgtable-bits.h inclusions
>   MIPS: Use enums to make asm/pgtable-bits.h readable
>   MIPS: mm: Standardise on _PAGE_NO_READ, drop _PAGE_READ
>   MIPS: mm: Unify pte_page definition
>   MIPS: mm: Fix MIPS32 36b physical addressing (alchemy, netlogic)
>   MIPS: mm: Pass scratch register through to iPTE_SW
>   MIPS: mm: Be more explicit about PTE mode bit handling
>   MIPS: mm: Simplify build_update_entries

Applied - but "MIPS: Separate XPA CPU feature into LPA and MVH" causes
a massive conflict with Florian's RIXI patches

  [3/6] MIPS: Allow RIXI to be used on non-R2 or R6 core
  [4/6] MIPS: Move RIXI exception enabling after vendor-specific cpu_probe
  [5/6] MIPS: BMIPS: BMIPS4380 and BMIPS5000 support RIXI

I figured unapplying those three, applying Paul's series then re-applying
Florian's patch on top of the whole series will be the easier path as in
leaving me with the smaller rejects to manage.

  Ralf