linux-kernel - [PATCH 1/1] perf/x86/intel: Change offcore response masks for Knights Landing

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Date:	Tue, 17 May 2016 09:43:21 +0200
From:	Lukasz Odzioba <lukasz.odzioba@...el.com>
To:	tglx@...utronix.de, mingo@...hat.com, hpa@...or.com,
	peterz@...radead.org, ak@...ux.intel.com, kan.liang@...el.com,
	akpm@...ux-foundation.org, eranian@...gle.com
Cc:	lukasz.anaczkowski@...el.com, lukasz.odzioba@...el.com,
	linux-kernel@...r.kernel.org
Subject: [PATCH 1/1] perf/x86/intel: Change offcore response masks for Knights Landing

Due to change in register definition we need to update OCR mask.
MSR_OFFCORE_RESP0 reserved bits: 3,4,18,29,30,33,34, 8,11,14
MSR_OFFCORE_RESP1 reserved bits: 3,4,18,29,30,33,34, 38

Reported-by: Andi Kleen <ak@...ux.intel.com>
Signed-off-by: Lukasz Odzioba <lukasz.odzioba@...el.com>
---
 arch/x86/events/intel/core.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index aff7988..23979de 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -186,10 +186,8 @@ struct event_constraint intel_skl_event_constraints[] = {
 };
 
 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
-	INTEL_UEVENT_EXTRA_REG(0x01b7,
-			       MSR_OFFCORE_RSP_0, 0x7f9ffbffffull, RSP_0),
-	INTEL_UEVENT_EXTRA_REG(0x02b7,
-			       MSR_OFFCORE_RSP_1, 0x3f9ffbffffull, RSP_1),
+	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
+	INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
 	EVENT_EXTRA_END
 };
 
-- 
1.8.3.1