linux-kernel - Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Tue, 24 May 2016 22:25:33 -0400
From:	Rich Felker <dalias@...c.org>
To:	Marc Zyngier <marc.zyngier@....com>
Cc:	Rob Herring <robh@...nel.org>, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-sh@...r.kernel.org,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Jason Cooper <jason@...edaemon.net>,
	Kumar Gala <galak@...eaurora.org>,
	Mark Rutland <mark.rutland@....com>,
	Pawel Moll <pawel.moll@....com>,
	Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings

On Tue, May 24, 2016 at 09:09:41AM +0100, Marc Zyngier wrote:
> On 23/05/16 22:13, Rich Felker wrote:
> > On Mon, May 23, 2016 at 03:53:20PM -0500, Rob Herring wrote:
> >> On Fri, May 20, 2016 at 02:53:04AM +0000, Rich Felker wrote:
> >>> Signed-off-by: Rich Felker <dalias@...c.org>
> >>> ---
> >>>  .../bindings/interrupt-controller/jcore,aic.txt    | 28 ++++++++++++++++++++++
> >>>  1 file changed, 28 insertions(+)
> >>>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> >>> new file mode 100644
> >>> index 0000000..dc9fde8
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> >>> @@ -0,0 +1,28 @@
> >>> +J-Core Advanced Interrupt Controller
> >>> +
> >>> +Required properties:
> >>> +
> >>> +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic
> >>> +  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> >>> +  the "aic2" core with 64 interrupts.
> >>> +
> >>> +- interrupt-controller : Identifies the node as an interrupt controller
> >>> +
> >>> +- #interrupt-cells : Specifies the number of cells needed to encode an
> >>> +  interrupt source. The value shall be 1.
> >>
> >> No level/edge support? Need 2 cells if so.
> > 
> > No, all the logic is in hardware. From the software side you just need
> > handle_simple_irq or equivalent.
> 
> Not even an EOI?

What I mean is that there is no ack/eoi interface. While I haven't
worked directly on the relevant vhdl, my understanding is that the aic
clears the pending status of an interrupt atomically with acceptance
of the interrupt by the cpu.

Do you have any more specific questions I can try to answer?

Rich