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Date:	Thu, 2 Jun 2016 10:54:25 +0200
From:	Peter Zijlstra <peterz@...radead.org>
To:	David Carrillo-Cisneros <davidcc@...gle.com>
Cc:	linux-kernel@...r.kernel.org, "x86@...nel.org" <x86@...nel.org>,
	Ingo Molnar <mingo@...hat.com>,
	"Yan, Zheng" <zheng.z.yan@...el.com>,
	Andi Kleen <ak@...ux.intel.com>,
	Kan Liang <kan.liang@...el.com>,
	Stephane Eranian <eranian@...gle.com>
Subject: Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk
 when no TSX

On Wed, Jun 01, 2016 at 07:42:02PM -0700, David Carrillo-Cisneros wrote:
> @@ -536,6 +597,7 @@ static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
>  	u64 br_type = event->attr.branch_sample_type;
>  	int mask = 0;
>  
> +
>  	if (br_type & PERF_SAMPLE_BRANCH_USER)
>  		mask |= X86_BR_USER;
>  

Do we really need this extra whitespace?

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