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Date: Mon, 13 Jun 2016 19:13:43 -0700 From: Doug Anderson <dianders@...omium.org> To: Shawn Lin <shawn.lin@...k-chips.com> Cc: Ulf Hansson <ulf.hansson@...aro.org>, Kishon Vijay Abraham I <kishon@...com>, Heiko Stuebner <heiko@...ech.de>, Rob Herring <robh+dt@...nel.org>, Ziyuan Xu <xzy.xu@...k-chips.com>, Brian Norris <briannorris@...omium.org>, Adrian Hunter <adrian.hunter@...el.com>, "open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>, "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>, "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>, Michal Simek <michal.simek@...inx.com>, soren.brinkmann@...inx.com, "linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org> Subject: Re: [PATCH 04/11] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 Shawn, On Mon, Jun 13, 2016 at 5:59 PM, Shawn Lin <shawn.lin@...k-chips.com> wrote: >> Even in the case that an SoC designer didn't put a value into >> corecfg_baseclkfreq that matched register[15:8], it seems very likely >> that the rate returned from the clk_get_rate() would match. >> >> I guess what I'm saying is that, to me, it seems like my patch isn't >> broken in any real systems. If we ever find a system that needs this >> behavior in the future, we can add it. Until then, it seems like my >> patch would be fine. Do you agree? > > > I agree. But from the code itself, we should still use > SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN to see if we could get > it from internal register in case of some platforms don't > provide the clk stuff.. Sounds sane? :) Could we wait until there exists a SoC that needs to provide baseclkfreq in its sdhci_arasan_soc_ctl_map table and that needs this value copied from register[15:8]? AKA: A) If you have a SoC where clk_get_rate() is right and software needs to set baseclkfreq manualy, then you should include "baseclkfreq" in your sdhci_arasan_soc_ctl_map table. This is like rk3399. Note that if _both_ clk_get_rate() and register[15:8] are right, that's fine. We can still use clk_get_rate() since it will be exactly the same as register[15:8]. B) If you have a SoC that doesn't even expose corecfg_baseclkfreq to software control, just don't include "baseclkfreq" in your sdhci_arasan_soc_ctl_map table. Easy. This is how my patch treats anyone using the current "generic" bindings, but you could easily just specify an offset of "-1" for baseclkfreq if you didn't want to use the generic bindings but couldn't control baseclkfreq. C) If you have a SoC that provides a valid value in register[15:8] and clk_get_rate() is wrong and software is required to copy the value from register[15:8] to baseclkfreq, technically we should fix clk_get_rate() anyway. It's good when common clock framework provides correct values. NOTE: It seems very unlikely to me that register[15:8] would be right AND that software would be required to copy this value to baseclkfreq, but I suppose there are some pretty crazy hardware designs out there. D) If you have a SoC that provides a valid value in register[15:8] and clk_get_rate() is wrong and can't be fixed (REALLY?) and software is required to copy the value from register[15:8] to baseclkfreq, we will need to add new code. My assertion is that such a SoC doesn't exist and is unlikely to ever exist, so I am hesitant to add extra code to support this SoC. With my patch, A) and B) are certainly handled. I think C) is unlikely to exist, but if it did exist then I'd say we should fix clk_get_rate(). I think D) is VERY unlikely to exist. If I'm shown proof of D) existing, I'm happy to submit a patch for it. Until we see proof of D)'s existence, I don't think we should clutter the code with support for it. -Doug
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