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Date: Thu, 28 Jul 2016 18:55:13 -0700 From: Andrey Pronin <apronin@...omium.org> To: Jarkko Sakkinen <jarkko.sakkinen@...ux.intel.com> Cc: Peter Huewe <peterhuewe@....de>, Marcel Selhorst <tpmdd@...horst.net>, Jason Gunthorpe <jgunthorpe@...idianresearch.com>, tpmdd-devel@...ts.sourceforge.net, linux-kernel@...r.kernel.org, Christophe Ricard <christophe.ricard@...il.com>, dtor@...omium.org, smbarber@...omium.org, dianders@...omium.org, Andrey Pronin <apronin@...omium.org>, Rob Herring <robh+dt@...nel.org>, Pawel Moll <pawel.moll@....com>, Mark Rutland <mark.rutland@....com>, Ian Campbell <ijc+devicetree@...lion.org.uk>, Kumar Gala <galak@...eaurora.org>, devicetree@...r.kernel.org Subject: [PATCH v4 1/2] tpm: devicetree: document properties for cr50 Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 firmware. Signed-off-by: Andrey Pronin <apronin@...omium.org> --- .../devicetree/bindings/security/tpm/cr50_spi.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/security/tpm/cr50_spi.txt diff --git a/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt new file mode 100644 index 0000000..2fbebd3 --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt @@ -0,0 +1,21 @@ +* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus. + +H1 Secure Microcontroller running Cr50 firmware provides several +functions, including TPM-like functionality. It communicates over +SPI using the FIFO protocol described in the PTP Spec, section 6. + +Required properties: +- compatible: Should be "google,cr50". +- spi-max-frequency: Maximum SPI frequency. + +Example: + +&spi0 { + status = "okay"; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + spi-max-frequency = <800000>; + }; +}; -- 2.6.6
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