linux-kernel - Re: [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433

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Message-ID: <CA+Ln22ESSK2tK=jiRU94H=sFz23Eoh0Z96k3rBoaz9xnZS9iJg@mail.gmail.com>
Date:	Tue, 16 Aug 2016 15:42:38 +0900
From:	Tomasz Figa <tomasz.figa@...il.com>
To:	Chanwoo Choi <cw00.choi@...sung.com>
Cc:	Krzysztof Kozłowski <k.kozlowski@...sung.com>,
	Kukjin Kim <kgene@...nel.org>,
	Rob Herring <robh+dt@...nel.org>,
	Mark Rutland <mark.rutland@....com>,
	Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will.deacon@....com>,
	devicetree <devicetree@...r.kernel.org>,
	linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
	"linux-samsung-soc@...r.kernel.org" 
	<linux-samsung-soc@...r.kernel.org>,
	linux-kernel <linux-kernel@...r.kernel.org>,
	Krzysztof Kozlowski <krzk@...nel.org>,
	Jaehoon Chung <jh80.chung@...sung.com>,
	"sw0312.kim" <sw0312.kim@...sung.com>,
	Joonyoung Shim <jy0922.shim@...sung.com>,
	InKi Dae <inki.dae@...sung.com>,
	Jonghwa Lee <jonghwa3.lee@...sung.com>,
	Beomho Seo <beomho.seo@...sung.com>, jaewon02.kim@...sung.com,
	human.hwang@...sung.com, Inha Song <ideal.song@...sung.com>,
	ingi2.kim@...sung.com, Marek Szyprowski <m.szyprowski@...sung.com>,
	Andrzej Hajda <a.hajda@...sung.com>,
	Sylwester Nawrocki <s.nawrocki@...sung.com>,
	chanwoo@...nel.org, Linus Walleij <linus.walleij@...aro.org>,
	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>
Subject: Re: [PATCH 4/7] pinctrl: samsung: Add GPFx support of Exynos5433

Hi,

2016-08-16 15:27 GMT+09:00 Chanwoo Choi <cw00.choi@...sung.com>:
> From: Joonyoung Shim <jy0922.shim@...sung.com>
>
> This patch add the support of GPFx pin of Exynos5433 SoC. Exynos5433 has
> different memory map of GPFx from previous Exynos SoC. Exynos GPIO has
> following register to control gpio funciton. Usually, all registers of GPIO
> are included in same domain.
> - CON / DAT / PUD / DRV / CONPDN / PUDPDN
> - EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND
>
> But, GPFx are included in two domain as following. So, this patch supports
> the GPFx pin which handle the on separate two domains.
> - ALIVE domain : CON / DAT / PUD / DRV / CONPDN / PUDPDN
> - IMEM domain  : EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND

I'm afraid I don't get anything from the description above. Could you
describe the layout of registers in memory map and IRQ routing of the
pins?

Best regards,
Tomasz