linux-kernel - [PATCH 00/10] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 31 Aug 2016 11:44:29 +0100
From:   Matt Redfearn <matt.redfearn@...tec.com>
To:     Ralf Baechle <ralf@...ux-mips.org>
CC:     <linux-mips@...ux-mips.org>,
        Matt Redfearn <matt.redfearn@...tec.com>,
        Arnd Bergmann <arnd@...db.de>, Tony Wu <tung7970@...il.com>,
        Nikolay Martynov <mar.kolya@...il.com>,
        Masahiro Yamada <yamada.masahiro@...ionext.com>,
        Kees Cook <keescook@...omium.org>, <linux-pm@...r.kernel.org>,
        Qais Yousef <qsyousef@...il.com>,
        <linux-kernel@...r.kernel.org>,
        "Michael S. Tsirkin" <mst@...hat.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        "Rafael J. Wysocki" <rjw@...ysocki.net>,
        James Hogan <james.hogan@...tec.com>,
        Andrew Morton <akpm@...ux-foundation.org>,
        Markos Chandras <markos.chandras@...tec.com>,
        Adam Buchbinder <adam.buchbinder@...il.com>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>,
        Paul Burton <paul.burton@...tec.com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>
Subject: [PATCH 00/10] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs

This series fixes a small issue with the CPC driver when A CM3 is
present, where a redundant lock was taken.

There are then additions to the pm-cps driver to add support for R6 CPUs
such as the I6400, and additionally the CM3 present in the I6400.

Finally we enable the cpuidle-cps driver for MIPSr6 CPUs.

Applies atop v4.8-rc4

Matt Redfearn (10):
  MIPS: CPC: Convert bare 'unsigned' to 'unsigned int'
  MIPS: CPC: Avoid lock when MIPS CM >= 3 is present
  MIPS: pm-cps: Change FSB workaround to CPU blacklist
  MIPS: pm-cps: Remove I6400 sync types
  MIPS: pm-cps: Add P6600 implementation lightweight sync types
  MIPS: pm-cps: Use MIPS standard lightweight ordering barrier
  MIPS: pm-cps: Add MIPSr6 CPU support
  MIPS: pm-cps: Support CM3 changes to Coherence Enable Register
  MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other
  cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs.

 arch/mips/include/asm/barrier.h | 10 ++++++
 arch/mips/include/asm/mips-cm.h |  1 +
 arch/mips/include/asm/pm-cps.h  |  6 ++--
 arch/mips/kernel/mips-cpc.c     | 17 +++++++++--
 arch/mips/kernel/pm-cps.c       | 67 ++++++++++++++++++++++++-----------------
 arch/mips/kernel/smp.c          |  2 ++
 drivers/cpuidle/Kconfig.mips    |  2 +-
 drivers/cpuidle/cpuidle-cps.c   |  2 +-
 8 files changed, 73 insertions(+), 34 deletions(-)

-- 
2.7.4