linux-kernel - Re: [PATCH 1/6] clk: sunxi-ng: div: Add mux table macros

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Fri, 2 Sep 2016 15:25:14 +0800
From:   Chen-Yu Tsai <wens@...e.org>
To:     Maxime Ripard <maxime.ripard@...e-electrons.com>
Cc:     Mike Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...eaurora.org>,
        Chen-Yu Tsai <wens@...e.org>,
        Hans de Goede <hdegoede@...hat.com>,
        Mylene Josserand <mylene.josserand@...e-electrons.com>,
        linux-clk <linux-clk@...r.kernel.org>,
        devicetree <devicetree@...r.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
Subject: Re: [PATCH 1/6] clk: sunxi-ng: div: Add mux table macros

On Thu, Sep 1, 2016 at 10:16 PM, Maxime Ripard
<maxime.ripard@...e-electrons.com> wrote:
> Add some macros to ease the declaration of clocks that are using them.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@...e-electrons.com>

Acked-by: Chen-Yu Tsai <wens@...e.org>

> ---
>  drivers/clk/sunxi-ng/ccu_div.h | 28 +++++++++++++++++++++-------
>  1 file changed, 21 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h
> index 5d98549e23a6..a5c9eaf90e84 100644
> --- a/drivers/clk/sunxi-ng/ccu_div.h
> +++ b/drivers/clk/sunxi-ng/ccu_div.h
> @@ -77,13 +77,16 @@ struct ccu_div {
>                                       _shift, _width, _table, 0,        \
>                                       _flags)
>
> -#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg,      \
> -                                 _mshift, _mwidth, _muxshift, _muxwidth, \
> -                                 _gate, _flags)                        \
> +#define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name,                        \
> +                                       _parents, _table,               \
> +                                       _reg,                           \
> +                                       _mshift, _mwidth,               \
> +                                       _muxshift, _muxwidth,           \
> +                                       _gate, _flags)                  \
>         struct ccu_div _struct = {                                      \
>                 .enable = _gate,                                        \
>                 .div    = _SUNXI_CCU_DIV(_mshift, _mwidth),             \
> -               .mux    = _SUNXI_CCU_MUX(_muxshift, _muxwidth),         \
> +               .mux    = _SUNXI_CCU_MUX_TABLE(_muxshift, _muxwidth, _table), \
>                 .common = {                                             \
>                         .reg            = _reg,                         \
>                         .hw.init        = CLK_HW_INIT_PARENTS(_name,    \
> @@ -93,12 +96,23 @@ struct ccu_div {
>                 },                                                      \
>         }
>
> +#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg,      \
> +                                 _mshift, _mwidth, _muxshift, _muxwidth, \
> +                                 _gate, _flags)                        \
> +       SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name,                 \
> +                                       _parents, NULL,                 \
> +                                       _reg, _mshift, _mwidth,         \
> +                                       _muxshift, _muxwidth,           \
> +                                       _gate, _flags)
> +
>  #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg,           \
>                              _mshift, _mwidth, _muxshift, _muxwidth,    \
>                              _flags)                                    \
> -       SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg,       \
> -                                 _mshift, _mwidth, _muxshift, _muxwidth, \
> -                                 0, _flags)
> +       SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name,                 \
> +                                       _parents, NULL,                 \
> +                                       _reg, _mshift, _mwidth,         \
> +                                       _muxshift, _muxwidth,           \
> +                                       0, _flags)

You probably didn't need to change this one though.

>
>
>  #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg,           \
> --
> 2.9.2
>