linux-kernel - [PATCH] clk: meson: fix CLKID_GCLK_VENCI

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Date:   Tue,  6 Sep 2016 15:01:10 +0200
From:   Arnd Bergmann <arnd@...db.de>
To:     Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...eaurora.org>
Cc:     Arnd Bergmann <arnd@...db.de>, Carlo Caione <carlo@...one.org>,
        Kevin Hilman <khilman@...libre.com>,
        Alexander Müller <serveralex@...il.com>,
        Paul Gortmaker <paul.gortmaker@...driver.com>,
        linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-amlogic@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH] clk: meson: fix CLKID_GCLK_VENCI_INT typo

The addition of many gate clocks added two entries in an array for
the same value:

drivers/clk/meson/meson8b.c:479:10: error: initialized field overwritten [-Werror=override-init]
   [CLKID_GCLK_VENCI_INT]     = &meson8b_gclk_venci_int.hw,
   [CLKID_GCLK_VENCI_INT]     = &meson8b_gclk_vencp_int.hw,

This was clearly an accident, and since all other identifiers are
listed in the order in which they are defined, I'm changing the
first one to CLKID_GCLK_VENCI_INT0, making it all consistent again.

Signed-off-by: Arnd Bergmann <arnd@...db.de>
Fixes: e31a1900c1ff ("meson: clk: Add support for clock gates")
---
 drivers/clk/meson/meson8b.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index e1d4aa145a03..0d45ec20c737 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -476,7 +476,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
 		[CLKID_VCLK2_VENCP0]	    = &meson8b_vclk2_vencp0.hw,
 		[CLKID_VCLK2_VENCP1]	    = &meson8b_vclk2_vencp1.hw,
 		[CLKID_GCLK_VENCI_INT]	    = &meson8b_gclk_venci_int.hw,
-		[CLKID_GCLK_VENCI_INT]	    = &meson8b_gclk_vencp_int.hw,
+		[CLKID_GCLK_VENCP_INT]	    = &meson8b_gclk_vencp_int.hw,
 		[CLKID_DAC_CLK]		    = &meson8b_dac_clk.hw,
 		[CLKID_AOCLK_GATE]	    = &meson8b_aoclk_gate.hw,
 		[CLKID_IEC958_GATE]	    = &meson8b_iec958_gate.hw,
-- 
2.9.0