linux-kernel - RE: [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support

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Date:   Fri, 9 Sep 2016 06:55:30 +0000
From:   "S.H. Xie" <shaohui.xie@....com>
To:     Mark Rutland <mark.rutland@....com>
CC:     "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "catalin.marinas@....com" <catalin.marinas@....com>,
        "will.deacon@....com" <will.deacon@....com>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "arnd@...db.de" <arnd@...db.de>, Vincent Hu <mingkai.hu@....com>,
        Horia Geanta Neag <horia.geanta@....com>,
        "Mihai Emilian Bantea" <mihai.bantea@....com>,
        "C.H. Zhao" <chenhui.zhao@....com>,
        "Q.Y. Gong" <qianyu.gong@....com>,
        "M.H. Lian" <minghuan.lian@....com>,
        "Z.Q. Hou" <zhiqiang.hou@....com>
Subject: RE: [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support

> On Thu, Sep 08, 2016 at 02:13:26PM +0100, Mark Rutland wrote:
> > On Mon, Sep 05, 2016 at 06:01:31PM +0800, shh.xie@...il.com wrote:
> > > +	cpus {
> > > +		#address-cells = <1>;
> > > +		#size-cells = <0>;
> > > +
> > > +		cpu0: cpu@0 {
> > > +			device_type = "cpu";
> > > +			compatible = "arm,cortex-a72";
> > > +			reg = <0x0>;
> > > +			clocks = <&clockgen 1 0>;
> > > +			next-level-cache = <&l2>;
> > > +			cpu-idle-states = <&CPU_PH20>;
> > > +		};
> >
> > [...]
> >
> > > +	};
> > > +
> > > +	idle-states {
> > > +		entry-method = "arm,psci";
> > > +
> > > +		CPU_PH20: cpu-ph20 {
> > > +			compatible = "arm,idle-state";
> > > +			idle-state-name = "PH20";
> > > +			arm,psci-suspend-param = <0x00010000>;
> > > +			entry-latency-us = <1000>;
> > > +			exit-latency-us = <1000>;
> > > +			min-residency-us = <3000>;
> > > +		};
> > > +	};
> >
> > There's no PSCI node in this file, and none from am included file, so
> > this doesn't look right.
> 
> Looking again, none of the cpu nodes has an enable-method property, and
> subsequent patches don't seem to add that to any cpu node.
> 
> Has this DT actually been tested?
[S.H] The PSCI node and the enable-method property are added by U-boot. 
U-boot can determine if using PSCI. If U-boot enables PSCI, it will add these 
missed parts in the dts. If not, it will not add these missed parts, 
so kernel will not use PSCI.

In other words, the dts does not enable PSCI by default. 
It's U-boot which adds the missed part if it determines to use PSCI.

Thanks,
Shaohui