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Date: Sat, 10 Sep 2016 01:53:58 +0800
From: Harry Pan <harry.pan@...el.com>
To: LKML <linux-kernel@...r.kernel.org>
Cc: gs0622@...il.com, Harry Pan <harry.pan@...el.com>,
tglx@...utronix.de, mingo@...hat.com, hpa@...or.com,
x86@...nel.org, peterz@...radead.org, bp@...en8.de,
ray.huang@....com, srinivas.pandruvada@...ux.intel.com
Subject: [PATCH 2/2] perf/x86/rapl: Enable Baytrail/Braswell RAPL support
This patch enables RAPL counters (energy consumption counters)
support for Intel Baytrail and Braswell processors (Model 55 and 76):
The Silvermont/Airmont microarchitecture actually uses fixed
energy status unit (ESU) in smallest unit of microjoule,
this patch adds quirk for these Atom processors (BYT/BSW)
to calculate energy increment in 2^ESU microjoules.
ESU and power domains refer to Intel Software Developers' Manual,
Vol. 3C, Order No. 325384, Table 35-8.
v2: simplify setting rapl_hw_unit[] to reduce runtime overhead.
v3: refine multiple quirks in rapl_check_hw_unit().
Usage example:
$ perf list
$ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10
This patch also enables multiple quirks.
Signed-off-by: Harry Pan <harry.pan@...el.com>
---
arch/x86/events/intel/rapl.c | 83 +++++++++++++++++++++++++++++++++++---------
1 file changed, 67 insertions(+), 16 deletions(-)
diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c
index f7924640..3786574 100644
--- a/arch/x86/events/intel/rapl.c
+++ b/arch/x86/events/intel/rapl.c
@@ -110,6 +110,10 @@ static const char *const rapl_domain_names[NR_RAPL_DOMAINS] __initconst = {
#define RAPL_IDX_KNL (1<<RAPL_IDX_PKG_NRG_STAT|\
1<<RAPL_IDX_RAM_NRG_STAT)
+/* Baytrail/Braswell clients have PP0, PKG */
+#define RAPL_IDX_BYT (1<<RAPL_IDX_PP0_NRG_STAT|\
+ 1<<RAPL_IDX_PKG_NRG_STAT)
+
/*
* event code: LSB 8 bits, passed in attr->config
* any other bit is reserved
@@ -136,6 +140,12 @@ static struct perf_pmu_events_attr event_attr_##v = { \
.event_str = str, \
};
+enum rapl_quirk {
+ RAPL_NO_QUIRK = 0,
+ RAPL_HSX_QUIRK,
+ RAPL_BYT_QUIRK,
+};
+
struct rapl_pmu {
raw_spinlock_t lock;
int n_active;
@@ -452,6 +462,14 @@ RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890
RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10");
RAPL_EVENT_ATTR_STR(energy-psys.scale, rapl_psys_scale, "2.3283064365386962890625e-10");
+/*
+ * Some Atom series processors (BYT/BSW) have fixed
+ * energy status unit (ESU) in smallest unit of microjoule,
+ * and its increment is in 2^ESU microjoules.
+ */
+RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_byt_cores_scale, "1.0e-6");
+RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_byt_pkg_scale, "1.0e-6");
+
static struct attribute *rapl_events_srv_attr[] = {
EVENT_PTR(rapl_cores),
EVENT_PTR(rapl_pkg),
@@ -533,6 +551,18 @@ static struct attribute *rapl_events_knl_attr[] = {
NULL,
};
+static struct attribute *rapl_events_byt_attr[] = {
+ EVENT_PTR(rapl_cores),
+ EVENT_PTR(rapl_pkg),
+
+ EVENT_PTR(rapl_cores_unit),
+ EVENT_PTR(rapl_pkg_unit),
+
+ EVENT_PTR(rapl_byt_cores_scale),
+ EVENT_PTR(rapl_byt_pkg_scale),
+ NULL,
+};
+
static struct attribute_group rapl_pmu_events_group = {
.name = "events",
.attrs = NULL, /* patched at runtime */
@@ -617,7 +647,7 @@ static int rapl_cpu_prepare(unsigned int cpu)
return 0;
}
-static int rapl_check_hw_unit(bool apply_quirk)
+static int rapl_check_hw_unit(enum rapl_quirk apply_quirk)
{
u64 msr_rapl_power_unit_bits;
int i;
@@ -628,14 +658,27 @@ static int rapl_check_hw_unit(bool apply_quirk)
for (i = 0; i < NR_RAPL_DOMAINS; i++)
rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL;
- /*
- * DRAM domain on HSW server and KNL has fixed energy unit which can be
- * different than the unit from power unit MSR. See
- * "Intel Xeon Processor E5-1600 and E5-2600 v3 Product Families, V2
- * of 2. Datasheet, September 2014, Reference Number: 330784-001 "
- */
- if (apply_quirk)
+ switch (apply_quirk) {
+ case RAPL_HSX_QUIRK:
+ /*
+ * DRAM domain on HSW server and KNL has fixed energy unit
+ * which can be different than the unit from power unit MSR.
+ * See "Intel Xeon Processor E5-1600 and E5-2600 v3 Product
+ * Families, V2 of 2. Datasheet, September 2014,
+ * Reference Number: 330784-001"
+ */
rapl_hw_unit[RAPL_IDX_RAM_NRG_STAT] = 16;
+ break;
+ case RAPL_BYT_QUIRK:
+ /*
+ * Some Atom processors (BYT/BSW) have 2^ESU microjoules
+ * increment, refer to Software Developers' Manual, Vol. 3C,
+ * Order No. 325384, Table 35-8 of MSR_RAPL_POWER_UNIT.
+ */
+ for (i = 0; i < NR_RAPL_DOMAINS; i++)
+ rapl_hw_unit[i] = 32 - rapl_hw_unit[i];
+ break;
+ }
/*
* Calculate the timer rate:
@@ -702,47 +745,53 @@ static int __init init_rapl_pmus(void)
{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&init }
struct intel_rapl_init_fun {
- bool apply_quirk;
+ enum rapl_quirk apply_quirk;
int cntr_mask;
struct attribute **attrs;
};
static const struct intel_rapl_init_fun snb_rapl_init __initconst = {
- .apply_quirk = false,
+ .apply_quirk = RAPL_NO_QUIRK,
.cntr_mask = RAPL_IDX_CLN,
.attrs = rapl_events_cln_attr,
};
static const struct intel_rapl_init_fun hsx_rapl_init __initconst = {
- .apply_quirk = true,
+ .apply_quirk = RAPL_HSX_QUIRK,
.cntr_mask = RAPL_IDX_SRV,
.attrs = rapl_events_srv_attr,
};
static const struct intel_rapl_init_fun hsw_rapl_init __initconst = {
- .apply_quirk = false,
+ .apply_quirk = RAPL_NO_QUIRK,
.cntr_mask = RAPL_IDX_HSW,
.attrs = rapl_events_hsw_attr,
};
static const struct intel_rapl_init_fun snbep_rapl_init __initconst = {
- .apply_quirk = false,
+ .apply_quirk = RAPL_NO_QUIRK,
.cntr_mask = RAPL_IDX_SRV,
.attrs = rapl_events_srv_attr,
};
static const struct intel_rapl_init_fun knl_rapl_init __initconst = {
- .apply_quirk = true,
+ .apply_quirk = RAPL_HSX_QUIRK,
.cntr_mask = RAPL_IDX_KNL,
.attrs = rapl_events_knl_attr,
};
static const struct intel_rapl_init_fun skl_rapl_init __initconst = {
- .apply_quirk = false,
+ .apply_quirk = RAPL_NO_QUIRK,
.cntr_mask = RAPL_IDX_SKL_CLN,
.attrs = rapl_events_skl_attr,
};
+static const struct intel_rapl_init_fun byt_rapl_init __initconst = {
+ .apply_quirk = RAPL_BYT_QUIRK,
+ .cntr_mask = RAPL_IDX_BYT,
+ .attrs = rapl_events_byt_attr,
+};
+
static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
X86_RAPL_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE, snb_rapl_init),
X86_RAPL_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE_X, snbep_rapl_init),
@@ -766,6 +815,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP, skl_rapl_init),
X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_X, hsx_rapl_init),
+ X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_SILVERMONT1, byt_rapl_init),
+ X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_AIRMONT, byt_rapl_init),
X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),
{},
};
@@ -776,7 +827,7 @@ static int __init rapl_pmu_init(void)
{
const struct x86_cpu_id *id;
struct intel_rapl_init_fun *rapl_init;
- bool apply_quirk;
+ enum rapl_quirk apply_quirk;
int ret;
id = x86_match_cpu(rapl_cpu_match);
--
2.6.6
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