linux-kernel - Re: [PATCH v3 2/3] ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support

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Date:   Sat, 10 Sep 2016 03:33:41 +0530
From:   Jagan Teki <jagan@...rulasolutions.com>
To:     Fabio Estevam <festevam@...il.com>
Cc:     Jagan Teki <jagannadh.teki@...il.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        Sascha Hauer <kernel@...gutronix.de>,
        Fabio Estevam <fabio.estevam@....com>,
        Shawn Guo <shawnguo@...nel.org>,
        Matteo Lisi <matteo.lisi@...icam.com>,
        Michael Trimarchi <michael@...rulasolutions.com>
Subject: Re: [PATCH v3 2/3] ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual
 initial support

On Sat, Sep 10, 2016 at 3:29 AM, Fabio Estevam <festevam@...il.com> wrote:
> On Fri, Sep 9, 2016 at 6:45 PM, Jagan Teki <jagannadh.teki@...il.com> wrote:
>
>> +&iomuxc {
>> +       pinctrl_flexcan1: flexcan1grp {
>> +               fsl,pins = <
>> +                       MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
>> +                       MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
>
> In the previous version you had "0x80000000", which means: use the pad
> value that comes from the bootloader.
>
> Does your bootloader configure the CAN pins? If not, then it should be
> 1b0b0, which is the POR value of register
> IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2.
>
> To confirm, you can do this in your bootloader:
>
> => md.l 20E05DC 1
> 020e05dc: 0001b0b0
>
> and see if returns 1b0b0 or 1b020.

Yeah, I got 1b0b0

U-Boot > md.l 20E05DC 1
020e05dc: 0001b0b0

thanks!
-- 
Jagan Teki
Free Software Engineer | Amarula Solutions
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.