Date:   Wed, 5 Oct 2016 13:18:05 +0530
From:   Anand Moon <linux.amoon@...il.com>
To:     Vivek Gautam <vivek.gautam@...eaurora.org>
Cc:     Michael Niewöhner <linux@...ewoehner.de>,
        Alim Akhtar <alim.akhtar@...sung.com>,
        Pankaj Dubey <pankaj.dubey@...sung.com>,
        Mathias Nyman <mathias.nyman@...ux.intel.com>,
        Felipe Balbi <balbi@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Kukjin Kim <kgene@...nel.org>,
        Krzysztof Kozlowski <k.kozlowski@...sung.com>,
        Linux USB Mailing List <linux-usb@...r.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        "linux-samsung-soc@...r.kernel.org" 
        <linux-samsung-soc@...r.kernel.org>,
        Linux Kernel <linux-kernel@...r.kernel.org>,
        Vivek Gautam <gautam.vivek@...sung.com>
Subject: Re: PROBLEM: DWC3 USB 3.0 not working on Odroid-XU4 with Exynos 5422

Hi Vivek,

On 5 October 2016 at 10:15, Vivek Gautam <vivek.gautam@...eaurora.org> wrote:
> Hi Anand,
>
>
> On Tue, Oct 4, 2016 at 8:39 PM, Anand Moon <linux.amoon@...il.com> wrote:
>> Hi Vivek,
>>
>
> [snip]
>
>>
>> What I feel is that their need to be some reset of usb phy so that
>> device are assigned to respective bus ports.
>
> The phy resets are what we do in the phy-exynos5-usbdrd driver. In
> addition to what we
> have currently in this phy driver, we just need the phy calibration
> patch [1] for phy configurations.
>
> [1] https://lkml.org/lkml/2015/2/2/259

Yes I am only using the above patch.
If you dont mind please resend this patch again.

>
>> odroid@...oid:~$ lsusb -t
>> /:  Bus 06.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 5000M
>> /:  Bus 05.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 480M
>>     |__ Port 1: Dev 3, If 0, Class=Vendor Specific Class, Driver=r8152, 480M
>
> This shows the ethernet device gets detected on the high-speed port of one
> of the controller.
> The lsusb output for kernel v4.7.x posted by Michael show that the
> ethernet device got detected on super-speed port of the controller.
> So, there seems to be a difference between the two.
> Or, is this how it is behaving ?

With other patches it miss behaves and the ethernet land onto another bus
port
.


> Is this lsusb output on 4.8 kernel with the patch [1] ?

Yes correct.

>
>> /:  Bus 04.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 5000M
>>     |__ Port 1: Dev 2, If 0, Class=Hub, Driver=hub/2p, 5000M
>>         |__ Port 1: Dev 3, If 0, Class=Mass Storage, Driver=usb-storage, 5000M
>>         |__ Port 2: Dev 4, If 0, Class=Mass Storage, Driver=usb-storage, 5000M
>> /:  Bus 03.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 480M
>>     |__ Port 1: Dev 2, If 0, Class=Hub, Driver=hub/2p, 480M
>> /:  Bus 02.Port 1: Dev 1, Class=root_hub, Driver=exynos-ohci/3p, 12M
>> /:  Bus 01.Port 1: Dev 1, Class=root_hub, Driver=exynos-ehci/3p, 480M
>>     |__ Port 1: Dev 3, If 0, Class=Mass Storage, Driver=usb-storage, 480M
>>
>>
>> Bus 06.Port should register the Realtek Ethernet r8153 device.
>> But I am not able to trace out how it's should happen.
>
> If i understand, below is how the configuration looks like on the board?
>
>                 +-----------------------+
>         +------>|                       |
>         |       |       Bus 6           |-------+
> +-----------+   |    (super-speed)      |       |
> |           |   +-----------------------+       |
> |Controller |                                   | --------> Ethernet device
> |    2      |                                   |
> |           |   +-----------------------+       |
> +-----------+   |                       |       |
>         |       |       Bus 5           |-------+
>         +------>|   (high-speed)        |
>                 +-----------------------+
>
>
>                 +-----------------------+
>         +------>|                       |
>         |       |       Bus 4           |-------+
> +-----------+   |    (super-speed)      |       |
> |           |   +-----------------------+       |
> |Controller |                                   | --------> (On board
> hub ?? _OR_ external hub with downstream devices) ???
> |    1      |                                   |
> |           |   +-----------------------+       |
> +-----------+   |                       |       |
>         |       |       Bus 3           |-------+
>         +------>|   (high-speed)        |
>                 +-----------------------+
>
[snip]

Yes this is correct mapping of usb ports and ethernet on the board.

Below is the schematic of the board.

http://dn.odroid.com/5422/ODROID-XU4/Schematics/XU4_MAIN_REV0.1_20151202.pdf

I have couple of questions so if you can help me out.

1 > Their is no vbus pin connector to the usb ports ?

2 > I have also tried to configure usbdrd_dwc3_0/1 nodes with no luck
                        snps,usb3_lpm_capable;
                        snps,dis_u3_susphy_quirk;
                        snps,dis_u2_susphy_quirk;

3 > do you feel their could be way to reset the USB PHY (ethenet)
       either though the DTS using gpio and pincrt

4 > how should be the port mapping done to the usb hub.
      Odroid XU4 has 2 usb 3.0 and 1 ehci port.
      Odroid XU3 has 1 usb 3.0 and 1 usb 3.0 otg port and 4 ehci
port


I would like to know how to debug low level debug of USB connection.
so that we could solve the issue.

Thanks for you help in looking to this, please guide me.
Attach is the logs of lsusb -v and console output.

-Best Regards
Anand Moon

View attachment "odroidxu4_lsusb.txt" of type "text/plain" (67003 bytes)

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