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Date:   Sat, 15 Oct 2016 09:39:24 -0700
From:   okaya@...eaurora.org
To:     Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com>
Cc:     Marc Zyngier <marc.zyngier@....com>, linux-pci@...r.kernel.org,
        linux-kernel@...r.kernel.org, Bjorn Helgaas <helgaas@...nel.org>,
        arnd@...db.de, linux-pci-owner@...r.kernel.org
Subject: Re: Why MSI is limited to 32 interrupts maximum

On 2016-10-15 06:30, Bharat Kumar Gogada wrote:
>> On Sat, 15 Oct 2016 12:37:55 +0000
>> Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com> wrote:
>> 
>> Hi Bharat,
>> 
>> > Can anyone tell why MSI interrupts are limited to maximum 32
>> > interrupts, even though we have 16bit message data register ?
>> 
>> That's the very definition of the original PCI MSI: Up to 32 
>> consecutive interrupts
>> per function, and a single doorbell address.
>> MSI-X lifts that restriction and offers up to 2048 interrupts that do 
>> not have to
>> be contiguous can target individual doorbells. Assuming your MSI 
>> controller
>> advertises MSI-X support and that your devices do support it as well, 
>> you'll be
>> able to enjoy those.
>> 
> 
> Thanks Marc, so then only 5 bits of message data register will be
> used, so what is the purpose rest of the bits ?
> 

Data field is used to indicate which interrupt number is used. It does 
not need to start at 0.


You have 32 consecutive interrupts starting from some arbitrary base.


>> >
>> > Regards,
>> > Bharat
>> >
>> >
>> > This email and any attachments are intended for the sole use of the
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>> >
>> 
>> Please fix your email not to carry such disclaimer (or use a private 
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>> if you can't work around your company policy). Posting confidential 
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>> 
>> Thanks,
>> 
>> 	M.
>> --
>> Without deviation from the norm, progress is not possible.
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