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Date:   Tue, 25 Oct 2016 16:01:07 +0300
From:   Stanimir Varbanov <stanimir.varbanov@...aro.org>
To:     Sricharan R <sricharan@...eaurora.org>, sboyd@...eaurora.org,
        mturquette@...libre.com, linux-clk@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        rnayak@...eaurora.org, stanimir.varbanov@...aro.org
Subject: Re: [PATCH 1/3] clk: qcom: gdsc: Add support for gdscs with HW
 control

Hi Sricharan,

On 10/24/2016 01:18 PM, Sricharan R wrote:
> From: Rajendra Nayak <rnayak@...eaurora.org>
> 
> Some GDSCs might support a HW control mode, where in the power
> domain (gdsc) is brought in and out of low power state (while
> unsued) without any SW assistance, saving power.
> Such GDSCs can be configured in a HW control mode when powered on
> until they are explicitly requested to be powered off by software.
> 
> Signed-off-by: Rajendra Nayak <rnayak@...eaurora.org>
> Signed-off-by: Sricharan R <sricharan@...eaurora.org>
> ---
>  drivers/clk/qcom/gdsc.c | 15 +++++++++++++++
>  drivers/clk/qcom/gdsc.h |  1 +
>  2 files changed, 16 insertions(+)
> 
> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
> index f12d7b2..a5e1c8c 100644
> --- a/drivers/clk/qcom/gdsc.c
> +++ b/drivers/clk/qcom/gdsc.c
> @@ -55,6 +55,13 @@ static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
>  	return !!(val & PWR_ON_MASK);
>  }
>  
> +static int gdsc_hwctrl(struct gdsc *sc, bool en)
> +{
> +	u32 val = en ? HW_CONTROL_MASK : 0;
> +
> +	return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
> +}
> +
>  static int gdsc_toggle_logic(struct gdsc *sc, bool en)
>  {
>  	int ret;
> @@ -164,6 +171,10 @@ static int gdsc_enable(struct generic_pm_domain *domain)
>  	 */
>  	udelay(1);
>  
> +	/* Turn on HW trigger mode if supported */
> +	if (sc->flags & HW_CTRL)
> +		gdsc_hwctrl(sc, true);

Could you check gdsc_hwctrl() for an error.

<cut>

-- 
regards,
Stan

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