| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Fri, 28 Oct 2016 15:49:54 +0200
From: Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
To: tglx@...utronix.de, mingo@...hat.com, hpa@...or.com, x86@...nel.org
Cc: bp@...e.de, dave.hansen@...ux.intel.com, lukasz.daniluk@...el.com,
james.h.cownie@...el.com, jacob.jun.pan@...el.com,
Piotr.Luc@...el.com, linux-kernel@...r.kernel.org,
Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
Subject: [PATCH v7 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features
Add Intel Xeon Phi x200 (KnightsLanding) cpu feature - ring 3 monitor/mwait
Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 92a8308..eb88eeb 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -101,6 +101,7 @@
#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
+#define X86_FEATURE_PHIR3MWAIT ( 3*32+25) /* Xeon Phi x200 ring 3 MONITOR/MWAIT */
#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
--
2.5.1
Powered by blists - more mailing lists