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Date: Thu, 10 Nov 2016 18:47:30 -0800
From: Darren Hart <dvhart@...radead.org>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: Tan Jui Nee <jui.nee.tan@...el.com>,
mika.westerberg@...ux.intel.com, heikki.krogerus@...ux.intel.com,
andriy.shevchenko@...ux.intel.com, mingo@...hat.com,
"H. Peter Anvin" <hpa@...or.com>, x86@...nel.org,
ptyser@...-inc.com, lee.jones@...aro.org, linus.walleij@...aro.org,
linux-gpio@...r.kernel.org, LKML <linux-kernel@...r.kernel.org>,
jonathan.yong@...el.com, ong.hock.yu@...el.com,
Tony Luck <tony.luck@...el.com>,
wan.ahmad.zainie.wan.mohamad@...el.com, yunying.sun@...el.com
Subject: Re: [PATCH v9 1/6] x86/platform/p2sb: New Primary to Sideband bridge
support driver for Intel SOC's
On Tue, Nov 08, 2016 at 05:55:20PM +0100, Thomas Gleixner wrote:
> On Tue, 8 Nov 2016, Tan Jui Nee wrote:
> > There is already one and at least one more user coming which
> > require an access to Primary to Sideband bridge (P2SB) in order
> > to get IO or MMIO bar hidden by BIOS.
> > Create a driver to access P2SB for x86 devices.
> >
> > arch/x86/Kconfig | 4 ++
> > arch/x86/include/asm/p2sb.h | 27 +++++++++++
> > arch/x86/platform/intel/Makefile | 1 +
> > arch/x86/platform/intel/p2sb.c | 98 ++++++++++++++++++++++++++++++++++++++++
>
> This really has nothing to do with architecture. It's a platform enablement
> driver and therefor should go into drivers/platform/x86
>
> Cc'ed Darren who is responsible for this.
Thanks Thomas,
Tan Jui, I'll be on a short medical leave through Nov 28. In the meantime, Andy
Shevchenko (on Cc) will be taking the lead on drivers/platform/x86 patches.
Andy, please work with Tan Jui to update this change to apply to our tree.
Thanks,
--
Darren Hart
Intel Open Source Technology Center
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