linux-kernel - Re: [RFC PATCH] mfd: dt: Add Aspeed LPC binding

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Date:   Thu, 17 Nov 2016 10:30:46 +0100
From:   Linus Walleij <linus.walleij@...aro.org>
To:     Andrew Jeffery <andrew@...id.au>
Cc:     Arnd Bergmann <arnd@...db.de>, Lee Jones <lee.jones@...aro.org>,
        Benjamin Herrenschmidt <benh@...nel.crashing.org>,
        Joel Stanley <joel@....id.au>,
        Rob Herring <robh+dt@...nel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [RFC PATCH] mfd: dt: Add Aspeed LPC binding

On Thu, Nov 17, 2016 at 7:06 AM, Andrew Jeffery <andrew@...id.au> wrote:

> +* Device tree bindings for the Aspeed LPC Controller

We are going overboard with the lingo sometimes, to the point that we do not
understand how terse things become.

LPC = Low Pin Count, right?
Explain that right here: it is a slow external bus, right?

> +The Aspeed LPC controller contains registers for a variety of functions. Not
> +all registers for a function are contiguous, and some registers are referenced
> +by functions outside the LPC controller.
> +
> +Note that this is separate from the H8S/2168 compatible register set occupying
> +the start of the LPC controller address space.
> +
> +Some significant functions in the LPC controller:
> +
> +* LPC Host Controller
> +* Host Interface Controller

Host interface to what?

> +* iBT Controller

What is iBT?

> +* SuperIO Scratch registers

Again more context please.

With standards documents, either explain everything or provide
pointers for the information.

Yours,
Linus Walleij