lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Thu, 8 Dec 2016 17:34:33 +0100
From:   Robert Richter <robert.richter@...ium.com>
To:     Bjorn Helgaas <helgaas@...nel.org>
CC:     Tomasz Nowicki <tn@...ihalf.com>,
        Ard Biesheuvel <ard.biesheuvel@...aro.org>,
        Jayachandran C <jchandra@...adcom.com>,
        Gabriele Paoloni <gabriele.paoloni@...wei.com>,
        Arnd Bergmann <arnd@...db.de>,
        Rafael Wysocki <rafael@...nel.org>,
        <linux-pci@...r.kernel.org>, Jon Masters <jcm@...hat.com>,
        Duc Dang <dhdang@....com>, Will Deacon <will.deacon@....com>,
        David Daney <ddaney@...iumnetworks.com>,
        Jeremy Linton <jeremy.linton@....com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linaro ACPI Mailman List <linaro-acpi@...ts.linaro.org>,
        <linux-acpi@...r.kernel.org>,
        Christopher Covington <cov@...eaurora.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Marcin Wojtas <mw@...ihalf.com>,
        Andrea Gallo <andrea.gallo@...aro.org>,
        linux-arm <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [Linaro-acpi] [PATCH V1 1/2] PCI: thunder: Enable ACPI PCI
 controller for ThunderX pass2.x silicon version

On 02.12.16 10:27:43, Bjorn Helgaas wrote:
> On Fri, Dec 02, 2016 at 11:45:00AM +0100, Robert Richter wrote:
> > On 02.12.16 11:06:24, Tomasz Nowicki wrote:
> > > On 02.12.2016 07:42, Duc Dang wrote:
> > 
> > > >@@ -98,16 +98,16 @@ struct mcfg_fixup {
> > > >        { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY,                 \
> > > >        &pci_thunder_ecam_ops }
> > > >        /* SoC pass1.x */
> > > >-   THUNDER_PEM_QUIRK(2,  0),       /* off-chip devices */
> > > >-   THUNDER_PEM_QUIRK(2,  1),       /* off-chip devices */
> > > >-   THUNDER_ECAM_QUIRK(2,  0),
> > > >-   THUNDER_ECAM_QUIRK(2,  1),
> > > >-   THUNDER_ECAM_QUIRK(2,  2),
> > > >-   THUNDER_ECAM_QUIRK(2,  3),
> > > >-   THUNDER_ECAM_QUIRK(2, 10),
> > > >-   THUNDER_ECAM_QUIRK(2, 11),
> > > >-   THUNDER_ECAM_QUIRK(2, 12),
> > > >-   THUNDER_ECAM_QUIRK(2, 13),
> > > >+ THUNDER_PEM_QUIRK(2, 0UL),  /* off-chip devices */
> > > >+ THUNDER_PEM_QUIRK(2, 1UL),  /* off-chip devices */
> > > >+ THUNDER_ECAM_QUIRK(2, 0UL),
> > > >+ THUNDER_ECAM_QUIRK(2, 1UL),
> > > >+ THUNDER_ECAM_QUIRK(2, 2UL),
> > > >+ THUNDER_ECAM_QUIRK(2, 3UL),
> > > >+ THUNDER_ECAM_QUIRK(2, 10UL),
> > > >+ THUNDER_ECAM_QUIRK(2, 11UL),
> > > >+ THUNDER_ECAM_QUIRK(2, 12UL),
> > > >+ THUNDER_ECAM_QUIRK(2, 13UL),
> > > >
> > > 
> > > The UL suffix is needed for *THUNDER_PEM_QUIRK* only. THUNDER_ECAM_QUIRK is
> > > fine.
> > 
> > We should better make the type cast part of the macro.
> > 
> > + this:
> > 
> > ---
> > #define THUNDER_MCFG_RES(addr, node) \
> >        DEFINE_RES_MEM(addr + (node << 44), 0x39 * SZ_16M)
> > ---
> > 
> > The args in the macro need parentheses.
> 
> Would you mind sending me a little incremental patch doing what you
> want?  I could try myself, but since I don't have an arm64 cross-build
> setup, I'm working in the dark.

Your current branch looks good.

 5d06f9125ec0 PCI: Explain ARM64 ACPI/MCFG quirk Kconfig and build strategy

Thanks,

-Robert

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ