lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Mon, 12 Dec 2016 13:33:53 +0000
From:   Juri Lelli <juri.lelli@....com>
To:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>
Cc:     linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        peterz@...radead.org, vincent.guittot@...aro.org,
        robh+dt@...nel.org, mark.rutland@....com, linux@....linux.org.uk,
        sudeep.holla@....com, catalin.marinas@....com, will.deacon@....com,
        morten.rasmussen@....com, dietmar.eggemann@....com,
        broonie@...nel.org, Pawel Moll <pawel.moll@....com>,
        Ian Campbell <ijc+devicetree@...lion.org.uk>,
        Kumar Gala <galak@...eaurora.org>,
        Maxime Ripard <maxime.ripard@...e-electrons.com>,
        Olof Johansson <olof@...om.net>,
        Gregory CLEMENT <gregory.clement@...e-electrons.com>,
        Paul Walmsley <paul@...an.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Chen-Yu Tsai <wens@...e.org>,
        Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
Subject: Re: [PATCH v7 1/8] Documentation: arm: define DT cpu
 capacity-dmips-mhz bindings

On 12/12/16 12:40, Lorenzo Pieralisi wrote:
> On Mon, Sep 05, 2016 at 03:22:45PM +0100, Juri Lelli wrote:
> 
> [...]
> 
> > +===========================================
> > +5 - References
> > +===========================================
> > +
> > +[1] ARM Linux Kernel documentation - CPUs bindings
> > +    Documentation/devicetree/bindings/arm/cpus.txt
> > diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> > index e6782d50cbcd..c1dcf4cade2e 100644
> > --- a/Documentation/devicetree/bindings/arm/cpus.txt
> > +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> > @@ -241,6 +241,14 @@ nodes to be present and contain the properties described below.
> >  			# List of phandles to idle state nodes supported
> >  			  by this cpu [3].
> >  
> > +	- capacity-dmips-mhz
> > +		Usage: Optional
> > +		Value type: <u32>
> > +		Definition:
> > +			# u32 value representing CPU capacity [3] in
> > +			  DMIPS/MHz, relative to highest capacity-dmips-mhz
> > +			  in the system.
> > +
> >  	- rockchip,pmu
> >  		Usage: optional for systems that have an "enable-method"
> >  		       property value of "rockchip,rk3066-smp"
> > @@ -464,3 +472,5 @@ cpus {
> >  [2] arm/msm/qcom,kpss-acc.txt
> >  [3] ARM Linux kernel documentation - idle states bindings
> >      Documentation/devicetree/bindings/arm/idle-states.txt
> > +[3] ARM Linux kernel documentation - cpu capacity bindings
> > +    Documentation/devicetree/bindings/arm/cpu-capacity.txt
> 
> Trivia: bumped into this while reviewing something else, too many
> threes, you will have to fix the added reference up.

Argh! Fixed locally, thanks for catching it.

Best,

- Juri

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ