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Date:   Sat, 31 Dec 2016 13:53:51 +0100
From:   Heiko Stuebner <heiko@...ech.de>
To:     Elaine Zhang <zhangqing@...k-chips.com>
Cc:     mturquette@...libre.com, sboyd@...eaurora.org, xf@...k-chips.com,
        robh+dt@...nel.org, mark.rutland@....com,
        linux-clk@...r.kernel.org, huangtao@...k-chips.com,
        xxx@...k-chips.com, cl@...k-chips.com,
        linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v5 3/4] clk: rockchip: add new pll-type for rk3328

Am Donnerstag, 29. Dezember 2016, 10:45:10 CET schrieb Elaine Zhang:
> The rk3328's pll and clock are similar with rk3036's,
> it different with pll_mode_mask, the rk3328 soc
> pll mode only one bit(rk3036 soc have two bits)
> so these should be independent and separate from
> the series of rk3328s.
> 
> Changes in v4:
>   adjust the pacth 3 and 4 order.
>   move pll_rk3328 to patch 3.
> Changes in v3:
>   fix up the pll type pll_rk3328 description and use
> 
> Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com>

applied to my clk-branch for 4.11

The clock controller itself also looks good now, I'll just give Rob or someone 
else a bit of time for eventual comments after new years :-)

Heiko

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