lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Thu, 19 Jan 2017 12:15:56 +0200
From:   Adrian Hunter <adrian.hunter@...el.com>
To:     Ritesh Harjani <riteshh@...eaurora.org>, ulf.hansson@...aro.org
Cc:     linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
        shawn.lin@...k-chips.com, linux-arm-msm@...r.kernel.org,
        georgi.djakov@...aro.org, asutoshd@...eaurora.org,
        stummala@...eaurora.org, venkatg@...eaurora.org,
        pramod.gurav@...aro.org, jeremymc@...hat.com, git@...r.de
Subject: Re: [RESEND PATCHv1 7/8] mmc: sdhci-msm: Make HS400 tuning follow as
 per recommeneded HW sequence

On 10/01/17 09:00, Ritesh Harjani wrote:
> During tuning execution for HS400 mode, HW sequence recommends
> to select MCLK_SEL/2(0x3) in VENDOR_SPEC & sdhc msm clock at GCC
> to be 400MHZ (nearest supported clk). Add this change in tuning
> sequence during HS400 tuning.
> 
> Signed-off-by: Ritesh Harjani <riteshh@...eaurora.org>

You may need to re-base this if you make changes as per patch 6, but otherwise:

Acked-by: Adrian Hunter <adrian.hunter@...el.com>

> ---
>  drivers/mmc/host/sdhci-msm.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 84d29dd..fa9bce3 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -151,7 +151,8 @@ static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
>  	 */
>  	if (ios.timing == MMC_TIMING_UHS_DDR50 ||
>  	    ios.timing == MMC_TIMING_MMC_DDR52 ||
> -	    ios.timing == MMC_TIMING_MMC_HS400)
> +	    ios.timing == MMC_TIMING_MMC_HS400 ||
> +	    host->flags & SDHCI_HS400_TUNING)
>  		clock *= 2;
>  	return clock;
>  }
> @@ -611,7 +612,8 @@ void sdhci_msm_hc_select_mode(struct sdhci_host *host)
>  {
>  	struct mmc_ios ios = host->mmc->ios;
>  
> -	if (ios.timing == MMC_TIMING_MMC_HS400)
> +	if (ios.timing == MMC_TIMING_MMC_HS400 ||
> +	    host->flags & SDHCI_HS400_TUNING)
>  		msm_hc_select_hs400(host);
>  	else
>  		msm_hc_select_default(host);
> @@ -831,6 +833,16 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
>  	    ios.timing == MMC_TIMING_UHS_SDR104))
>  		return 0;
>  
> +	/*
> +	 * For HS400 tuning in HS200 timing requires:
> +	 * - select MCLK/2 in VENDOR_SPEC
> +	 * - program MCLK to 400MHz (or nearest supported) in GCC
> +	 */
> +	if (host->flags & SDHCI_HS400_TUNING) {
> +		sdhci_msm_hc_select_mode(host);
> +		msm_set_clock_rate_for_bus_mode(host, ios.clock);
> +	}
> +
>  retry:
>  	/* First of all reset the tuning block */
>  	rc = msm_init_cm_dll(host);
> 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ