lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Sat, 21 Jan 2017 16:41:12 +0530
From:   Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com>
To:     <bhelgaas@...gle.com>, <paul.gortmaker@...driver.com>,
        <robh@...nel.org>, <colin.king@...onical.com>,
        <linux-pci@...r.kernel.org>, <marc.zyngier@....com>
CC:     <michal.simek@...inx.com>, <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <rgummal@...inx.com>,
        <arnd@...db.de>, Bharat Kumar Gogada <bharatku@...inx.com>
Subject: [PATCH 4/4] PCI: Xilinx NWL: Fix, proc interrupts for legacy virtual irq shown as edge

- Legacy interrupts are level triggered, virtual irq line of End
Point shows as edge.
- Setting irq flags of virtual irq line of EP to level triggered
at the time of mapping.

Signed-off-by: Bharat Kumar Gogada <bharatku@...inx.com>
---
 drivers/pci/host/pcie-xilinx-nwl.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c
index 50f9c0d..b7aa6f8 100644
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -435,6 +435,7 @@ static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
 {
 	irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq);
 	irq_set_chip_data(irq, domain->host_data);
+	irq_set_status_flags(irq, IRQ_LEVEL);
 
 	return 0;
 }
-- 
1.7.1

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ