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Date: Mon, 6 Feb 2017 12:32:34 +0800
From: kbuild test robot <fengguang.wu@...el.com>
To: Ingo Molnar <mingo@...nel.org>
Cc: kbuild-all@...org, linux-kernel@...r.kernel.org, tipbuild@...or.com
Subject: [tip:WIP.sched/core 138/162] arch/mips/kernel/smp-bmips.c:183:22:
note: in expansion of macro '__KSTK_TOS'
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git WIP.sched/core
head: 38c7fc1c938c469af27c032bf4eab0c4aaf4eba1
commit: f05fc91845e26cd4d605aeb77b1901b8eb9471b5 [138/162] sched/headers: Split <linux/sched/task_stack> out of <linux/sched.h>
config: mips-bmips_be_defconfig (attached as .config)
compiler: mips-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout f05fc91845e26cd4d605aeb77b1901b8eb9471b5
# save the attached .config to linux build tree
make.cross ARCH=mips
All warnings (new ones prefixed by >>):
In file included from arch/mips/include/asm/thread_info.h:15:0,
from include/linux/thread_info.h:25,
from include/asm-generic/preempt.h:4,
from ./arch/mips/include/generated/asm/preempt.h:1,
from include/linux/preempt.h:80,
from include/linux/spinlock.h:50,
from include/linux/mm_types.h:8,
from include/linux/sched.h:9,
from arch/mips/kernel/smp-bmips.c:12:
arch/mips/kernel/smp-bmips.c: In function 'bmips_boot_secondary':
arch/mips/include/asm/processor.h:384:41: error: implicit declaration of function 'task_stack_page' [-Werror=implicit-function-declaration]
#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
^
>> arch/mips/kernel/smp-bmips.c:183:22: note: in expansion of macro '__KSTK_TOS'
bmips_smp_boot_sp = __KSTK_TOS(idle);
^~~~~~~~~~
cc1: some warnings being treated as errors
vim +/__KSTK_TOS +183 arch/mips/kernel/smp-bmips.c
df0ac8a40 Kevin Cernekee 2011-11-16 6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@...il.com)
df0ac8a40 Kevin Cernekee 2011-11-16 7 *
df0ac8a40 Kevin Cernekee 2011-11-16 8 * SMP support for BMIPS
df0ac8a40 Kevin Cernekee 2011-11-16 9 */
df0ac8a40 Kevin Cernekee 2011-11-16 10
df0ac8a40 Kevin Cernekee 2011-11-16 11 #include <linux/init.h>
df0ac8a40 Kevin Cernekee 2011-11-16 @12 #include <linux/sched.h>
960c8706e Ingo Molnar 2017-02-03 13 #include <linux/sched/hotplug.h>
df0ac8a40 Kevin Cernekee 2011-11-16 14 #include <linux/mm.h>
df0ac8a40 Kevin Cernekee 2011-11-16 15 #include <linux/delay.h>
df0ac8a40 Kevin Cernekee 2011-11-16 16 #include <linux/smp.h>
df0ac8a40 Kevin Cernekee 2011-11-16 17 #include <linux/interrupt.h>
df0ac8a40 Kevin Cernekee 2011-11-16 18 #include <linux/spinlock.h>
df0ac8a40 Kevin Cernekee 2011-11-16 19 #include <linux/cpu.h>
df0ac8a40 Kevin Cernekee 2011-11-16 20 #include <linux/cpumask.h>
df0ac8a40 Kevin Cernekee 2011-11-16 21 #include <linux/reboot.h>
df0ac8a40 Kevin Cernekee 2011-11-16 22 #include <linux/io.h>
df0ac8a40 Kevin Cernekee 2011-11-16 23 #include <linux/compiler.h>
df0ac8a40 Kevin Cernekee 2011-11-16 24 #include <linux/linkage.h>
df0ac8a40 Kevin Cernekee 2011-11-16 25 #include <linux/bug.h>
df0ac8a40 Kevin Cernekee 2011-11-16 26 #include <linux/kernel.h>
df0ac8a40 Kevin Cernekee 2011-11-16 27
df0ac8a40 Kevin Cernekee 2011-11-16 28 #include <asm/time.h>
df0ac8a40 Kevin Cernekee 2011-11-16 29 #include <asm/pgtable.h>
df0ac8a40 Kevin Cernekee 2011-11-16 30 #include <asm/processor.h>
df0ac8a40 Kevin Cernekee 2011-11-16 31 #include <asm/bootinfo.h>
df0ac8a40 Kevin Cernekee 2011-11-16 32 #include <asm/pmon.h>
df0ac8a40 Kevin Cernekee 2011-11-16 33 #include <asm/cacheflush.h>
df0ac8a40 Kevin Cernekee 2011-11-16 34 #include <asm/tlbflush.h>
df0ac8a40 Kevin Cernekee 2011-11-16 35 #include <asm/mipsregs.h>
df0ac8a40 Kevin Cernekee 2011-11-16 36 #include <asm/bmips.h>
df0ac8a40 Kevin Cernekee 2011-11-16 37 #include <asm/traps.h>
df0ac8a40 Kevin Cernekee 2011-11-16 38 #include <asm/barrier.h>
fc4557879 Kevin Cernekee 2014-10-20 39 #include <asm/cpu-features.h>
df0ac8a40 Kevin Cernekee 2011-11-16 40
df0ac8a40 Kevin Cernekee 2011-11-16 41 static int __maybe_unused max_cpus = 1;
df0ac8a40 Kevin Cernekee 2011-11-16 42
df0ac8a40 Kevin Cernekee 2011-11-16 43 /* these may be configured by the platform code */
df0ac8a40 Kevin Cernekee 2011-11-16 44 int bmips_smp_enabled = 1;
df0ac8a40 Kevin Cernekee 2011-11-16 45 int bmips_cpu_offset;
df0ac8a40 Kevin Cernekee 2011-11-16 46 cpumask_t bmips_booted_mask;
d8010ceba Kevin Cernekee 2014-10-20 47 unsigned long bmips_tp1_irqs = IE_IRQ1;
df0ac8a40 Kevin Cernekee 2011-11-16 48
fc4557879 Kevin Cernekee 2014-10-20 49 #define RESET_FROM_KSEG0 0x80080800
fc4557879 Kevin Cernekee 2014-10-20 50 #define RESET_FROM_KSEG1 0xa0080800
fc4557879 Kevin Cernekee 2014-10-20 51
3677a2836 Kevin Cernekee 2014-10-20 52 static void bmips_set_reset_vec(int cpu, u32 val);
3677a2836 Kevin Cernekee 2014-10-20 53
df0ac8a40 Kevin Cernekee 2011-11-16 54 #ifdef CONFIG_SMP
df0ac8a40 Kevin Cernekee 2011-11-16 55
df0ac8a40 Kevin Cernekee 2011-11-16 56 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
df0ac8a40 Kevin Cernekee 2011-11-16 57 unsigned long bmips_smp_boot_sp;
df0ac8a40 Kevin Cernekee 2011-11-16 58 unsigned long bmips_smp_boot_gp;
df0ac8a40 Kevin Cernekee 2011-11-16 59
6465460c9 Jonas Gorski 2013-12-18 60 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
6465460c9 Jonas Gorski 2013-12-18 61 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
6465460c9 Jonas Gorski 2013-12-18 62 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
6465460c9 Jonas Gorski 2013-12-18 63 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
df0ac8a40 Kevin Cernekee 2011-11-16 64
df0ac8a40 Kevin Cernekee 2011-11-16 65 /* SW interrupts 0,1 are used for interprocessor signaling */
df0ac8a40 Kevin Cernekee 2011-11-16 66 #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
df0ac8a40 Kevin Cernekee 2011-11-16 67 #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
df0ac8a40 Kevin Cernekee 2011-11-16 68
df0ac8a40 Kevin Cernekee 2011-11-16 69 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
df0ac8a40 Kevin Cernekee 2011-11-16 70 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
df0ac8a40 Kevin Cernekee 2011-11-16 71 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
df0ac8a40 Kevin Cernekee 2011-11-16 72 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
df0ac8a40 Kevin Cernekee 2011-11-16 73
df0ac8a40 Kevin Cernekee 2011-11-16 74 static void __init bmips_smp_setup(void)
df0ac8a40 Kevin Cernekee 2011-11-16 75 {
4df715aaf Florian Fainelli 2013-06-26 76 int i, cpu = 1, boot_cpu = 0;
fcfa66de8 Florian Fainelli 2013-08-05 77 int cpu_hw_intr;
fcfa66de8 Florian Fainelli 2013-08-05 78
6465460c9 Jonas Gorski 2013-12-18 79 switch (current_cpu_type()) {
6465460c9 Jonas Gorski 2013-12-18 80 case CPU_BMIPS4350:
6465460c9 Jonas Gorski 2013-12-18 81 case CPU_BMIPS4380:
df0ac8a40 Kevin Cernekee 2011-11-16 82 /* arbitration priority */
df0ac8a40 Kevin Cernekee 2011-11-16 83 clear_c0_brcm_cmt_ctrl(0x30);
df0ac8a40 Kevin Cernekee 2011-11-16 84
df0ac8a40 Kevin Cernekee 2011-11-16 85 /* NBK and weak order flags */
df0ac8a40 Kevin Cernekee 2011-11-16 86 set_c0_brcm_config_0(0x30000);
df0ac8a40 Kevin Cernekee 2011-11-16 87
4df715aaf Florian Fainelli 2013-06-26 88 /* Find out if we are running on TP0 or TP1 */
4df715aaf Florian Fainelli 2013-06-26 89 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
4df715aaf Florian Fainelli 2013-06-26 90
df0ac8a40 Kevin Cernekee 2011-11-16 91 /*
6465460c9 Jonas Gorski 2013-12-18 92 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
6465460c9 Jonas Gorski 2013-12-18 93 * thread
df0ac8a40 Kevin Cernekee 2011-11-16 94 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
df0ac8a40 Kevin Cernekee 2011-11-16 95 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
df0ac8a40 Kevin Cernekee 2011-11-16 96 */
fcfa66de8 Florian Fainelli 2013-08-05 97 if (boot_cpu == 0)
fcfa66de8 Florian Fainelli 2013-08-05 98 cpu_hw_intr = 0x02;
fcfa66de8 Florian Fainelli 2013-08-05 99 else
fcfa66de8 Florian Fainelli 2013-08-05 100 cpu_hw_intr = 0x1d;
fcfa66de8 Florian Fainelli 2013-08-05 101
6465460c9 Jonas Gorski 2013-12-18 102 change_c0_brcm_cmt_intr(0xf8018000,
6465460c9 Jonas Gorski 2013-12-18 103 (cpu_hw_intr << 27) | (0x03 << 15));
df0ac8a40 Kevin Cernekee 2011-11-16 104
df0ac8a40 Kevin Cernekee 2011-11-16 105 /* single core, 2 threads (2 pipelines) */
df0ac8a40 Kevin Cernekee 2011-11-16 106 max_cpus = 2;
6465460c9 Jonas Gorski 2013-12-18 107
6465460c9 Jonas Gorski 2013-12-18 108 break;
6465460c9 Jonas Gorski 2013-12-18 109 case CPU_BMIPS5000:
df0ac8a40 Kevin Cernekee 2011-11-16 110 /* enable raceless SW interrupts */
df0ac8a40 Kevin Cernekee 2011-11-16 111 set_c0_brcm_config(0x03 << 22);
df0ac8a40 Kevin Cernekee 2011-11-16 112
df0ac8a40 Kevin Cernekee 2011-11-16 113 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
df0ac8a40 Kevin Cernekee 2011-11-16 114 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
df0ac8a40 Kevin Cernekee 2011-11-16 115
df0ac8a40 Kevin Cernekee 2011-11-16 116 /* N cores, 2 threads per core */
df0ac8a40 Kevin Cernekee 2011-11-16 117 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
df0ac8a40 Kevin Cernekee 2011-11-16 118
df0ac8a40 Kevin Cernekee 2011-11-16 119 /* clear any pending SW interrupts */
df0ac8a40 Kevin Cernekee 2011-11-16 120 for (i = 0; i < max_cpus; i++) {
df0ac8a40 Kevin Cernekee 2011-11-16 121 write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
df0ac8a40 Kevin Cernekee 2011-11-16 122 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
df0ac8a40 Kevin Cernekee 2011-11-16 123 }
6465460c9 Jonas Gorski 2013-12-18 124
6465460c9 Jonas Gorski 2013-12-18 125 break;
6465460c9 Jonas Gorski 2013-12-18 126 default:
6465460c9 Jonas Gorski 2013-12-18 127 max_cpus = 1;
6465460c9 Jonas Gorski 2013-12-18 128 }
df0ac8a40 Kevin Cernekee 2011-11-16 129
df0ac8a40 Kevin Cernekee 2011-11-16 130 if (!bmips_smp_enabled)
df0ac8a40 Kevin Cernekee 2011-11-16 131 max_cpus = 1;
df0ac8a40 Kevin Cernekee 2011-11-16 132
df0ac8a40 Kevin Cernekee 2011-11-16 133 /* this can be overridden by the BSP */
df0ac8a40 Kevin Cernekee 2011-11-16 134 if (!board_ebase_setup)
df0ac8a40 Kevin Cernekee 2011-11-16 135 board_ebase_setup = &bmips_ebase_setup;
df0ac8a40 Kevin Cernekee 2011-11-16 136
4df715aaf Florian Fainelli 2013-06-26 137 __cpu_number_map[boot_cpu] = 0;
4df715aaf Florian Fainelli 2013-06-26 138 __cpu_logical_map[0] = boot_cpu;
4df715aaf Florian Fainelli 2013-06-26 139
df0ac8a40 Kevin Cernekee 2011-11-16 140 for (i = 0; i < max_cpus; i++) {
4df715aaf Florian Fainelli 2013-06-26 141 if (i != boot_cpu) {
4df715aaf Florian Fainelli 2013-06-26 142 __cpu_number_map[i] = cpu;
4df715aaf Florian Fainelli 2013-06-26 143 __cpu_logical_map[cpu] = i;
4df715aaf Florian Fainelli 2013-06-26 144 cpu++;
4df715aaf Florian Fainelli 2013-06-26 145 }
df0ac8a40 Kevin Cernekee 2011-11-16 146 set_cpu_possible(i, 1);
df0ac8a40 Kevin Cernekee 2011-11-16 147 set_cpu_present(i, 1);
df0ac8a40 Kevin Cernekee 2011-11-16 148 }
df0ac8a40 Kevin Cernekee 2011-11-16 149 }
df0ac8a40 Kevin Cernekee 2011-11-16 150
df0ac8a40 Kevin Cernekee 2011-11-16 151 /*
df0ac8a40 Kevin Cernekee 2011-11-16 152 * IPI IRQ setup - runs on CPU0
df0ac8a40 Kevin Cernekee 2011-11-16 153 */
df0ac8a40 Kevin Cernekee 2011-11-16 154 static void bmips_prepare_cpus(unsigned int max_cpus)
df0ac8a40 Kevin Cernekee 2011-11-16 155 {
6465460c9 Jonas Gorski 2013-12-18 156 irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
6465460c9 Jonas Gorski 2013-12-18 157
6465460c9 Jonas Gorski 2013-12-18 158 switch (current_cpu_type()) {
6465460c9 Jonas Gorski 2013-12-18 159 case CPU_BMIPS4350:
6465460c9 Jonas Gorski 2013-12-18 160 case CPU_BMIPS4380:
6465460c9 Jonas Gorski 2013-12-18 161 bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
6465460c9 Jonas Gorski 2013-12-18 162 break;
6465460c9 Jonas Gorski 2013-12-18 163 case CPU_BMIPS5000:
6465460c9 Jonas Gorski 2013-12-18 164 bmips_ipi_interrupt = bmips5000_ipi_interrupt;
6465460c9 Jonas Gorski 2013-12-18 165 break;
6465460c9 Jonas Gorski 2013-12-18 166 default:
6465460c9 Jonas Gorski 2013-12-18 167 return;
6465460c9 Jonas Gorski 2013-12-18 168 }
6465460c9 Jonas Gorski 2013-12-18 169
df0ac8a40 Kevin Cernekee 2011-11-16 170 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
df0ac8a40 Kevin Cernekee 2011-11-16 171 "smp_ipi0", NULL))
f7777dcc7 Ralf Baechle 2013-09-18 172 panic("Can't request IPI0 interrupt");
df0ac8a40 Kevin Cernekee 2011-11-16 173 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
df0ac8a40 Kevin Cernekee 2011-11-16 174 "smp_ipi1", NULL))
f7777dcc7 Ralf Baechle 2013-09-18 175 panic("Can't request IPI1 interrupt");
df0ac8a40 Kevin Cernekee 2011-11-16 176 }
df0ac8a40 Kevin Cernekee 2011-11-16 177
df0ac8a40 Kevin Cernekee 2011-11-16 178 /*
df0ac8a40 Kevin Cernekee 2011-11-16 179 * Tell the hardware to boot CPUx - runs on CPU0
df0ac8a40 Kevin Cernekee 2011-11-16 180 */
df0ac8a40 Kevin Cernekee 2011-11-16 181 static void bmips_boot_secondary(int cpu, struct task_struct *idle)
df0ac8a40 Kevin Cernekee 2011-11-16 182 {
df0ac8a40 Kevin Cernekee 2011-11-16 @183 bmips_smp_boot_sp = __KSTK_TOS(idle);
df0ac8a40 Kevin Cernekee 2011-11-16 184 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
df0ac8a40 Kevin Cernekee 2011-11-16 185 mb();
df0ac8a40 Kevin Cernekee 2011-11-16 186
:::::: The code at line 183 was first introduced by commit
:::::: df0ac8a406718360aa08e632a73a805a6cc4cb27 MIPS: BMIPS: Add SMP support code for BMIPS43xx/BMIPS5000
:::::: TO: Kevin Cernekee <cernekee@...il.com>
:::::: CC: Ralf Baechle <ralf@...ux-mips.org>
---
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