linux-kernel - [PATCH 1/4] arm64: arch_timer: add dt binding for hisilicon-161010101 erratum

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Date:   Mon,  6 Feb 2017 16:47:39 +0000
From:   Mark Rutland <mark.rutland@....com>
To:     daniel.lezcano@...aro.org
Cc:     tglx@...utronix.de, mark.rutland@....com, marc.zyngier@....com,
        dingtianhong@...wei.com, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org
Subject: [PATCH 1/4] arm64: arch_timer: add dt binding for hisilicon-161010101 erratum

From: Ding Tianhong <dingtianhong@...wei.com>

This erratum describes a bug in logic outside the core, so MIDR can't be
used to identify its presence, and reading an SoC-specific revision
register from common arch timer code would be awkward.  So, describe it
in the device tree.

Signed-off-by: Ding Tianhong <dingtianhong@...wei.com>
Acked-by: Rob Herring <robh@...nel.org>
Signed-off-by: Mark Rutland <mark.rutland@....com>
---
 Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index ad440a2..e926aea 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -31,6 +31,12 @@ to deliver its interrupts via SPIs.
   This also affects writes to the tval register, due to the implicit
   counter read.
 
+- hisilicon,erratum-161010101 : A boolean property. Indicates the
+  presence of Hisilicon erratum 161010101, which says that reading the
+  counters is unreliable in some cases, and reads may return a value 32
+  beyond the correct value. This also affects writes to the tval
+  registers, due to the implicit counter read.
+
 ** Optional properties:
 
 - arm,cpu-registers-not-fw-configured : Firmware does not initialize
-- 
1.9.1