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Date: Thu, 2 Mar 2017 07:57:11 -0800
From: matthew.gerlach@...ux.intel.com
To: atull@...nsource.altera.com, moritz.fischer@...us.com,
linux-fpga@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, robh+dt@...nel.org,
mark.rutland@....com
Cc: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
Subject: [PATCH v4 3/4] fpga dt: bindings for Altera Partial Reconfiguration IP.
From: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
Device Tree bindings for Altera Partial Reconfiguration IP.
v3: s/altr,pr-ip/altr,a10-pr-ip/
v2: s/Reconfiguraion/Reconfiguration/
====================
Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
---
Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
1 file changed, 12 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
new file mode 100644
index 0000000..52a294c
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
@@ -0,0 +1,12 @@
+Altera Arria10 Partial Reconfiguration IP
+
+Required properties:
+- compatible : should contain "altr,a10-pr-ip"
+- reg : base address and size for memory mapped io.
+
+Example:
+
+ fpga_mgr: fpga-mgr@...0c000 {
+ compatible = "altr,a10-pr-ip";
+ reg = <0xff20c000 0x10>;
+ };
--
2.7.4
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