lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Sun, 2 Apr 2017 12:12:01 -0700
From:   tip-bot for Ravi Bangoria <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     mhiramat@...nel.org, linux-kernel@...r.kernel.org,
        alexander.shishkin@...ux.intel.com,
        ravi.bangoria@...ux.vnet.ibm.com, alexis.berlemont@...il.com,
        acme@...hat.com, peterz@...radead.org, tglx@...utronix.de,
        hemant@...ux.vnet.ibm.com, mingo@...nel.org, mpe@...erman.id.au,
        hpa@...or.com, naveen.n.rao@...ux.vnet.ibm.com
Subject: [tip:perf/core] perf/sdt/x86: Add renaming logic for (missing) 8
 bit registers

Commit-ID:  2d01ecc580405169ecd6e3880617bc61cf482fdd
Gitweb:     http://git.kernel.org/tip/2d01ecc580405169ecd6e3880617bc61cf482fdd
Author:     Ravi Bangoria <ravi.bangoria@...ux.vnet.ibm.com>
AuthorDate: Tue, 28 Mar 2017 15:17:52 +0530
Committer:  Arnaldo Carvalho de Melo <acme@...hat.com>
CommitDate: Tue, 28 Mar 2017 12:24:56 -0300

perf/sdt/x86: Add renaming logic for (missing) 8 bit registers

I found couple of events using al, bl, cl and dl registers for argument.
These are not directly accepted by uprobe_events and thus needs to be
mapped to ax, bx, cx and dx respectively.

Few ex,

  /usr/bin/qemu-system-s390x
    css_adapter_interrupt: 1@%bl
    css_chpid_add: 1@%cl 1@...l 1@%dl
    dma_bdrv_io: 8@...x 8@...p -8@...4 1@%al

  /usr/bin/postgres
    buffer__read__done: ... -1@...sh -1@%al
    buffer__read__start: ... -1@%al

I don't find any sdt events using ah, bh,... registers. But I also don't
see any reason to not use them, so there might be rare events using
these registers, and if so, perf should have a renaming logic for them
too.

Signed-off-by: Ravi Bangoria <ravi.bangoria@...ux.vnet.ibm.com>
Acked-by: Masami Hiramatsu <mhiramat@...nel.org>
Cc: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc: Alexis Berlemont <alexis.berlemont@...il.com>
Cc: Hemant Kumar <hemant@...ux.vnet.ibm.com>
Cc: Michael Ellerman <mpe@...erman.id.au>
Cc: Naveen N. Rao <naveen.n.rao@...ux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@...radead.org>
Link: http://lkml.kernel.org/r/20170328094754.3156-2-ravi.bangoria@linux.vnet.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@...hat.com>
---
 tools/perf/arch/x86/util/perf_regs.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/tools/perf/arch/x86/util/perf_regs.c b/tools/perf/arch/x86/util/perf_regs.c
index d8a8dcf..fa1fd19 100644
--- a/tools/perf/arch/x86/util/perf_regs.c
+++ b/tools/perf/arch/x86/util/perf_regs.c
@@ -40,12 +40,20 @@ struct sdt_name_reg {
 static const struct sdt_name_reg sdt_reg_renamings[] = {
 	SDT_NAME_REG(eax, ax),
 	SDT_NAME_REG(rax, ax),
+	SDT_NAME_REG(al,  ax),
+	SDT_NAME_REG(ah,  ax),
 	SDT_NAME_REG(ebx, bx),
 	SDT_NAME_REG(rbx, bx),
+	SDT_NAME_REG(bl,  bx),
+	SDT_NAME_REG(bh,  bx),
 	SDT_NAME_REG(ecx, cx),
 	SDT_NAME_REG(rcx, cx),
+	SDT_NAME_REG(cl,  cx),
+	SDT_NAME_REG(ch,  cx),
 	SDT_NAME_REG(edx, dx),
 	SDT_NAME_REG(rdx, dx),
+	SDT_NAME_REG(dl,  dx),
+	SDT_NAME_REG(dh,  dx),
 	SDT_NAME_REG(esi, si),
 	SDT_NAME_REG(rsi, si),
 	SDT_NAME_REG(sil, si),

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ