linux-kernel - Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

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Date:   Thu, 27 Apr 2017 18:00:31 +0100
From:   Will Deacon <will.deacon@....com>
To:     Mark Rutland <mark.rutland@....com>
Cc:     Geetha sowjanya <gakula@...iumnetworks.com>, robin.murphy@....com,
        lorenzo.pieralisi@....com, hanjun.guo@...aro.org,
        sudeep.holla@....com, iommu@...ts.linux-foundation.org,
        jcm@...hat.com, linu.cherian@...ium.com,
        linux-kernel@...r.kernel.org, geethasowjanya.akula@...il.com,
        linux-acpi@...r.kernel.org, robert.richter@...ium.com,
        catalin.marinas@....com, Geetha <gakula@...ium.com>,
        sgoutham@...ium.com, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium
 ThunderX2 erratum #74

On Thu, Apr 27, 2017 at 05:42:37PM +0100, Mark Rutland wrote:
> On Thu, Apr 27, 2017 at 05:16:23PM +0530, Geetha sowjanya wrote:
> > +	/*
> > +	 * Override the size, for Cavium CN99xx implementations
> > +	 * which doesn't support the page 1 SMMU register space.
> > +	 */
> > +	cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
> > +	if (cpu_model == MIDR_THUNDERX_99XX ||
> > +	    cpu_model == MIDR_BRCM_VULCAN)
> > +		size = SZ_64K;
> 
> If you're trying to identify an SMMU erratum, identify the SMMU, not the
> CPU it happens to be paired with this time.
> 
> There are ID registers in the SMMU you can use to do so.
> 
> NAK to using the CPU ID here.

Agreed. I had some off-list discussion with Geetha where we agreed to use
the "silicon ID", which I assumed was the SMMU IIDR register.

Will