linux-kernel - Re: [PATCH 3/4] KVM: x86: drop bogus MWAIT check

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Thu, 4 May 2017 21:26:32 +0300
From:   "Michael S. Tsirkin" <mst@...hat.com>
To:     Paolo Bonzini <pbonzini@...hat.com>
Cc:     Radim Krčmář <rkrcmar@...hat.com>,
        linux-kernel@...r.kernel.org, kvm@...r.kernel.org,
        Alexander Graf <agraf@...e.de>,
        "Gabriel L. Somlo" <gsomlo@...il.com>
Subject: Re: [PATCH 3/4] KVM: x86: drop bogus MWAIT check

On Thu, May 04, 2017 at 12:58:05PM +0200, Paolo Bonzini wrote:
> 
> 
> On 03/05/2017 21:37, Radim Krčmář wrote:
> > The guest can call MWAIT with ECX = 0 even if we enforce
> > CPUID5_ECX_INTERRUPT_BREAK;  the call would have the exactly the same
> > effect as if the host didn't have CPUID5_ECX_INTERRUPT_BREAK.
> > 
> > The check was added in some iteration while trying to fix a reported
> > OS X on Core 2 bug, but the CPU had CPUID5_ECX_INTERRUPT_BREAK and the
> > bug is elsewhere.
> 
> The reason for this, as I understood it, is that we have historically
> not published leaf 5 information via KVM_GET_SUPPORTED_CPUID.  For this
> reason, QEMU is publishing CPUID5_ECX_INTERRUPT_BREAK.  Then if:
> 
> - the host doesn't have ECX[0]=1 support
> 
> - the guest sets ECX[0]
> 
> you get a #GP in the guest.  So wrong comment but right thing to do.
> 
> Paolo

Exactly. And I agree the comment isn't a good one.



> > Signed-off-by: Radim Krčmář <rkrcmar@...hat.com>
> > ---
> >  arch/x86/kvm/x86.h | 23 +----------------------
> >  1 file changed, 1 insertion(+), 22 deletions(-)
> > 
> > diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h
> > index 63d5fb65ea30..8ea4e80c24d1 100644
> > --- a/arch/x86/kvm/x86.h
> > +++ b/arch/x86/kvm/x86.h
> > @@ -216,8 +216,6 @@ static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
> >  
> >  static inline bool kvm_mwait_in_guest(void)
> >  {
> > -	unsigned int eax, ebx, ecx, edx;
> > -
> >  	if (!cpu_has(&boot_cpu_data, X86_FEATURE_MWAIT))
> >  		return false;
> >  
> > @@ -225,29 +223,10 @@ static inline bool kvm_mwait_in_guest(void)
> >  	case X86_VENDOR_AMD:
> >  		return !boot_cpu_has_bug(X86_BUG_AMD_E400);
> >  	case X86_VENDOR_INTEL:
> > -		/* Handle Intel below */
> > -		break;
> > +		return !boot_cpu_has_bug(X86_BUG_MONITOR);
> >  	default:
> >  		return false;
> >  	}
> > -
> > -	if (boot_cpu_has_bug(X86_BUG_MONITOR))
> > -		return false;
> > -
> > -	/*
> > -	 * Intel CPUs without CPUID5_ECX_INTERRUPT_BREAK are problematic as
> > -	 * they would allow guest to stop the CPU completely by disabling
> > -	 * interrupts then invoking MWAIT.
> > -	 */
> > -	if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
> > -		return false;
> > -
> > -	cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
> > -
> > -	if (!(ecx & CPUID5_ECX_INTERRUPT_BREAK))
> > -		return false;
> > -
> > -	return true;
> >  }
> >  
> >  #endif
> >