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Date: Fri, 5 May 2017 11:31:49 +0800
From: Chen-Yu Tsai <wens@...e.org>
To: Icenowy Zheng <icenowy@...c.io>
Cc: Maxime Ripard <maxime.ripard@...e-electrons.com>,
Rob Herring <robh+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
linux-clk <linux-clk@...r.kernel.org>,
devicetree <devicetree@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
dri-devel <dri-devel@...ts.freedesktop.org>,
linux-sunxi <linux-sunxi@...glegroups.com>
Subject: Re: [linux-sunxi] [PATCH v6 11/13] ARM: dts: sun8i: add DE2 nodes for
V3s SoC
On Thu, May 4, 2017 at 7:48 PM, Icenowy Zheng <icenowy@...c.io> wrote:
> Allwinner V3s SoC features a "Display Engine 2.0" with only one TCON
> which have RGB LCD output.
Please also mention that it only has one mixer.
For the subject, you could just say "Add device nodes for the display pipeline".
>
> Add device nodes for it as well as the TCON.
>
> Signed-off-by: Icenowy Zheng <icenowy@...c.io>
> ---
> arch/arm/boot/dts/sun8i-v3s.dtsi | 87 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 87 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
> index 71075969e5e6..0a895179d8ae 100644
> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi
> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
> @@ -41,6 +41,10 @@
> */
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/sun8i-v3s-ccu.h>
> +#include <dt-bindings/clock/sun8i-de2.h>
> +#include <dt-bindings/reset/sun8i-v3s-ccu.h>
> +#include <dt-bindings/reset/sun8i-de2.h>
>
> / {
> #address-cells = <1>;
> @@ -59,6 +63,12 @@
> };
> };
>
> + de: display-engine {
> + compatible = "allwinner,sun8i-v3s-display-engine";
> + allwinner,pipelines = <&de2_mixer0>;
> + status = "disabled";
> + };
> +
> timer {
> compatible = "arm,armv7-timer";
> interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> @@ -93,6 +103,83 @@
> #size-cells = <1>;
> ranges;
>
> + de2_clocks: clock@...0000 {
> + compatible = "allwinner,sun50i-h5-de2-clk";
I am a bit skeptical about this. Since the V3S only has one mixer, do the clocks
for the second one even exist?
> + reg = <0x01000000 0x100000>;
> + clocks = <&ccu CLK_DE>,
> + <&ccu CLK_BUS_DE>;
> + clock-names = "mod",
> + "bus";
> + resets = <&ccu RST_BUS_DE>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + de2_mixer0: mixer@...0000 {
> + compatible = "allwinner,sun8i-v3s-de2-mixer";
> + reg = <0x01100000 0x100000>;
> + clocks = <&de2_clocks CLK_MIXER0>,
> + <&de2_clocks CLK_BUS_MIXER0>;
> + clock-names = "mod",
> + "bus";
Nit: could you list the bus clock first?
Regards
ChenYu
> + resets = <&de2_clocks RST_MIXER0>;
> + assigned-clocks = <&de2_clocks CLK_MIXER0>;
> + assigned-clock-rates = <150000000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mixer0_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + mixer0_out_tcon0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon0_in_mixer0>;
> + };
> + };
> + };
> + };
> +
> + tcon0: lcd-controller@...c000 {
> + compatible = "allwinner,sun8i-v3s-tcon";
> + reg = <0x01c0c000 0x1000>;
> + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_TCON0>,
> + <&ccu CLK_TCON0>;
> + clock-names = "ahb",
> + "tcon-ch0";
> + clock-output-names = "tcon-pixel-clock";
> + resets = <&ccu RST_BUS_TCON0>;
> + reset-names = "lcd";
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon0_in: port@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> +
> + tcon0_in_mixer0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&mixer0_out_tcon0>;
> + };
> + };
> +
> + tcon0_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + };
> + };
> + };
> +
> +
> mmc0: mmc@...0f000 {
> compatible = "allwinner,sun7i-a20-mmc";
> reg = <0x01c0f000 0x1000>;
> --
> 2.12.2
>
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