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Date:   Wed, 10 May 2017 20:23:22 -0700
From:   Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
To:     Paolo Bonzini <pbonzini@...hat.com>
Cc:     Ingo Molnar <mingo@...hat.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        "H. Peter Anvin" <hpa@...or.com>,
        Andy Lutomirski <luto@...nel.org>,
        Borislav Petkov <bp@...e.de>,
        Peter Zijlstra <peterz@...radead.org>,
        Andrew Morton <akpm@...ux-foundation.org>,
        Brian Gerst <brgerst@...il.com>,
        Chris Metcalf <cmetcalf@...lanox.com>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        Liang Z Li <liang.z.li@...el.com>,
        Masami Hiramatsu <mhiramat@...nel.org>,
        Huang Rui <ray.huang@....com>, Jiri Slaby <jslaby@...e.cz>,
        Jonathan Corbet <corbet@....net>,
        "Michael S. Tsirkin" <mst@...hat.com>,
        Paul Gortmaker <paul.gortmaker@...driver.com>,
        Vlastimil Babka <vbabka@...e.cz>,
        Chen Yucong <slaoub@...il.com>,
        Alexandre Julliard <julliard@...ehq.org>,
        Stas Sergeev <stsp@...t.ru>, Fenghua Yu <fenghua.yu@...el.com>,
        "Ravi V. Shankar" <ravi.v.shankar@...el.com>,
        Shuah Khan <shuah@...nel.org>, linux-kernel@...r.kernel.org,
        x86@...nel.org, linux-msdos@...r.kernel.org, wine-devel@...ehq.org,
        Tony Luck <tony.luck@...el.com>
Subject: Re: [PATCH v7 20/26] x86/cpufeature: Add User-Mode Instruction
 Prevention definitions

On Sat, 2017-05-06 at 11:04 +0200, Paolo Bonzini wrote:
> 
> 
> On 05/05/2017 20:17, Ricardo Neri wrote:
> > User-Mode Instruction Prevention is a security feature present in
> new
> > Intel processors that, when set, prevents the execution of a subset
> of
> > instructions if such instructions are executed in user mode (CPL >
> 0).
> > Attempting to execute such instructions causes a general protection
> > exception.
> > 
> > The subset of instructions comprises:
> > 
> >  * SGDT - Store Global Descriptor Table
> >  * SIDT - Store Interrupt Descriptor Table
> >  * SLDT - Store Local Descriptor Table
> >  * SMSW - Store Machine Status Word
> >  * STR  - Store Task Register
> > 
> > This feature is also added to the list of disabled-features to allow
> > a cleaner handling of build-time configuration.
> > 
> > Cc: Andy Lutomirski <luto@...nel.org>
> > Cc: Andrew Morton <akpm@...ux-foundation.org>
> > Cc: H. Peter Anvin <hpa@...or.com>
> > Cc: Borislav Petkov <bp@...e.de>
> > Cc: Brian Gerst <brgerst@...il.com>
> > Cc: Chen Yucong <slaoub@...il.com>
> > Cc: Chris Metcalf <cmetcalf@...lanox.com>
> > Cc: Dave Hansen <dave.hansen@...ux.intel.com>
> > Cc: Fenghua Yu <fenghua.yu@...el.com>
> > Cc: Huang Rui <ray.huang@....com>
> > Cc: Jiri Slaby <jslaby@...e.cz>
> > Cc: Jonathan Corbet <corbet@....net>
> > Cc: Michael S. Tsirkin <mst@...hat.com>
> > Cc: Paul Gortmaker <paul.gortmaker@...driver.com>
> > Cc: Peter Zijlstra <peterz@...radead.org>
> > Cc: Ravi V. Shankar <ravi.v.shankar@...el.com>
> > Cc: Shuah Khan <shuah@...nel.org>
> > Cc: Vlastimil Babka <vbabka@...e.cz>
> > Cc: Tony Luck <tony.luck@...el.com>
> > Cc: Paolo Bonzini <pbonzini@...hat.com>
> > Cc: Liang Z. Li <liang.z.li@...el.com>
> > Cc: Alexandre Julliard <julliard@...ehq.org>
> > Cc: Stas Sergeev <stsp@...t.ru>
> > Cc: x86@...nel.org
> > Cc: linux-msdos@...r.kernel.org
> > 
> > Signed-off-by: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
> 
> Would it be possible to have this patch in a topic branch for KVM's
> consumption?
> 
I have put a branch here with this single patch:

https://github.com/ricardon/tip.git rneri/umip_for_kvm

This is based on Linux v4.11. Please let me know if this works for your
or you'd prefer it to be based on a different branch/commit/repo.

Thanks and BR,
Ricardo

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