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Date: Thu, 11 May 2017 22:00:19 -0400 From: Len Brown <lenb@...nel.org> To: rjw@...ysocki.net, linux-pm@...r.kernel.org Cc: linux-kernel@...r.kernel.org, Len Brown <len.brown@...el.com> Subject: [PATCH 1/5] x86: msr-index.h: define EPB mid-points From: Len Brown <len.brown@...el.com> These are currently open-coded into intel_pstate.c Signed-off-by: Len Brown <len.brown@...el.com> --- arch/x86/include/asm/msr-index.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 710273c617b8..a92d9bd154f6 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -462,9 +462,11 @@ #define MSR_MISC_PWR_MGMT 0x000001aa #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 -#define ENERGY_PERF_BIAS_PERFORMANCE 0 -#define ENERGY_PERF_BIAS_NORMAL 6 -#define ENERGY_PERF_BIAS_POWERSAVE 15 +#define ENERGY_PERF_BIAS_PERFORMANCE 0 +#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 +#define ENERGY_PERF_BIAS_NORMAL 6 +#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 +#define ENERGY_PERF_BIAS_POWERSAVE 15 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 -- 2.11.0.161.g6610af872
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