linux-kernel - Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

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Date:   Wed, 17 May 2017 12:33:15 -0700
From:   Bjorn Andersson <bjorn.andersson@...aro.org>
To:     Varadarajan Narayanan <varada@...eaurora.org>
Cc:     robh+dt@...nel.org, mark.rutland@....com, mturquette@...libre.com,
        sboyd@...eaurora.org, linus.walleij@...aro.org,
        andy.gross@...aro.org, david.brown@...aro.org,
        catalin.marinas@....com, will.deacon@....com,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-gpio@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, absahu@...eaurora.org,
        sjaganat@...eaurora.org, sricharan@...eaurora.org,
        Manoharan Vijaya Raghavan <mraghava@...eaurora.org>
Subject: Re: [PATCH v2 1/5] pinctrl: qcom: Add ipq8074 pinctrl driver

On Mon 15 May 02:05 PDT 2017, Varadarajan Narayanan wrote:

> On 5/14/2017 9:53 AM, Bjorn Andersson wrote:
> > On Thu 11 May 03:33 PDT 2017, Varadarajan Narayanan wrote:
> > 
> > > On 5/11/2017 4:13 AM, Bjorn Andersson wrote:
> > > > On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:
[..]
> > > > > +	msm_mux_qpic_pad4,
> > > > 
> > > > What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions,
> > > > alternative muxings...?
> > > 
> > > This is for the NAND and LCD display. The pins listed are the 9 data pins.
> > > 
> > 
> > Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's
> > possible to reference a partial group in the DTS, if that's necessary)
> 
> There are two sets of 9 pins, either of which can go to NAND or LCD.
> Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b.
> Is that ok?
> 

So you have NAND and LCD hardware muxed to either "a" or "b" and then
you mux either "a" or "b" out onto actual pins?

How is this first mux configured?


I think the a/b scheme sounds reasonable, if above is how it works.

Regards,
Bjorn