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Date:   Mon, 29 May 2017 14:25:11 +0200
From:   Linus Walleij <linus.walleij@...aro.org>
To:     David Wu <david.wu@...k-chips.com>
Cc:     Heiko Stübner <heiko@...ech.de>,
        Tao Huang <huangtao@...k-chips.com>,
        Doug Anderson <dianders@...omium.org>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
        "linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 1/4] pinctrl: rockchip: Add iomux-route switching support

On Fri, May 26, 2017 at 9:20 AM, David Wu <david.wu@...k-chips.com> wrote:

> On the some rockchip SOCS, some things like rk3399 specific uart2 can use
> multiple pins. Somewhere between the pin io-cells and the uart it seems
> to have some sort of switch to decide to which pin to actually route the
> data.
>
> +-------+    +--------+  /- GPIO4_B0 (pinmux 2)
>
> | uart2 | -- | switch | --- GPIO4_C0 (pinmux 2)
>
> +-------+    +--------+  \- GPIO4_C3 (pinmux 2)
> (switch selects one of the 3 pins base on the GRF_SOC_CON7[BIT0, BIT1])
>
> The routing switch is determined by one pin of a specific group to be set
> to its special pinmux function. If the pinmux setting is wrong for that
> pin the ip block won't work correctly anyway.
>
> Signed-off-by: David Wu <david.wu@...k-chips.com>

Patch applied with Heiko's ACK.

Yours,
Linus Walleij

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