linux-kernel - [tip:perf/urgent] perf/x86/intel: Add 1G DTLB load/store miss support for SKL

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Thu, 22 Jun 2017 04:09:28 -0700
From:   tip-bot for Kan Liang <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     jolsa@...hat.com, alexander.shishkin@...ux.intel.com,
        tglx@...utronix.de, stable@...r.kernel.org,
        linux-kernel@...r.kernel.org, torvalds@...ux-foundation.org,
        Kan.liang@...el.com, peterz@...radead.org, mingo@...nel.org,
        acme@...hat.com, hpa@...or.com
Subject: [tip:perf/urgent] perf/x86/intel: Add 1G DTLB load/store miss
 support for SKL

Commit-ID:  fb3a5055cd7098f8d1dd0cd38d7172211113255f
Gitweb:     http://git.kernel.org/tip/fb3a5055cd7098f8d1dd0cd38d7172211113255f
Author:     Kan Liang <Kan.liang@...el.com>
AuthorDate: Mon, 19 Jun 2017 07:26:09 -0700
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Thu, 22 Jun 2017 11:07:08 +0200

perf/x86/intel: Add 1G DTLB load/store miss support for SKL

Current DTLB load/store miss events (0x608/0x649) only counts 4K,2M and
4M page size.
Need to extend the events to support any page size (4K/2M/4M/1G).

The complete DTLB load/store miss events are:

  DTLB_LOAD_MISSES.WALK_COMPLETED		0xe08
  DTLB_STORE_MISSES.WALK_COMPLETED		0xe49

Signed-off-by: Kan Liang <Kan.liang@...el.com>
Cc: <stable@...r.kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@...hat.com>
Cc: Jiri Olsa <jolsa@...hat.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: eranian@...gle.com
Link: http://lkml.kernel.org/r/20170619142609.11058-1-kan.liang@intel.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/events/intel/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index a6d91d4..110ce82 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -431,11 +431,11 @@ static __initconst const u64 skl_hw_cache_event_ids
  [ C(DTLB) ] = {
 	[ C(OP_READ) ] = {
 		[ C(RESULT_ACCESS) ] = 0x81d0,	/* MEM_INST_RETIRED.ALL_LOADS */
-		[ C(RESULT_MISS)   ] = 0x608,	/* DTLB_LOAD_MISSES.WALK_COMPLETED */
+		[ C(RESULT_MISS)   ] = 0xe08,	/* DTLB_LOAD_MISSES.WALK_COMPLETED */
 	},
 	[ C(OP_WRITE) ] = {
 		[ C(RESULT_ACCESS) ] = 0x82d0,	/* MEM_INST_RETIRED.ALL_STORES */
-		[ C(RESULT_MISS)   ] = 0x649,	/* DTLB_STORE_MISSES.WALK_COMPLETED */
+		[ C(RESULT_MISS)   ] = 0xe49,	/* DTLB_STORE_MISSES.WALK_COMPLETED */
 	},
 	[ C(OP_PREFETCH) ] = {
 		[ C(RESULT_ACCESS) ] = 0x0,