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Date:   Fri, 23 Jun 2017 14:54:28 -0500
From:   Rob Herring <robh@...nel.org>
To:     Florian Fainelli <f.fainelli@...il.com>
Cc:     linux-arm-kernel@...r.kernel.org,
        Mark Rutland <mark.rutland@....com>,
        Brian Norris <computersforpeace@...il.com>,
        Gregory Fong <gregory.0xf0@...il.com>,
        "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" 
        <bcm-kernel-feedback-list@...adcom.com>,
        Hauke Mehrtens <hauke@...ke-m.de>,
        Rafał Miłecki <zajec5@...il.com>,
        Ralf Baechle <ralf@...ux-mips.org>,
        Markus Mayer <mmayer@...adcom.com>,
        Arnd Bergmann <arnd@...db.de>, Eric Anholt <eric@...olt.net>,
        Justin Chen <justinpopo6@...il.com>,
        Doug Berger <opendmb@...il.com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        "moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        open list <linux-kernel@...r.kernel.org>,
        "open list:BROADCOM BCM47XX MIPS ARCHITECTURE" 
        <linux-mips@...ux-mips.org>, linux-pm@...r.kernerl.org,
        "Rafael J. Wysocki" <rjw@...ysocki.net>
Subject: Re: [PATCH 1/5] dt-bindings: Update Broadcom STB binding

On Fri, Jun 16, 2017 at 02:36:59PM -0700, Florian Fainelli wrote:
> Update the Broadcom STB binding document with new compatible strings for
> the DDR PHY and memory controller found on newer chips.

The subject should be more specific what this patch is doing.

> Signed-off-by: Florian Fainelli <f.fainelli@...il.com>
> ---
>  Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt
> index 0d0c1ae81bed..790e6b0b8306 100644
> --- a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt
> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt
> @@ -164,6 +164,8 @@ Control registers for this memory controller's DDR PHY.
>  
>  Required properties:
>  - compatible     : should contain one of these
> +	"brcm,brcmstb-ddr-phy-v71.1"
> +	"brcm,brcmstb-ddr-phy-v72.0"
>  	"brcm,brcmstb-ddr-phy-v225.1"
>  	"brcm,brcmstb-ddr-phy-v240.1"
>  	"brcm,brcmstb-ddr-phy-v240.2"
> @@ -184,7 +186,9 @@ Sequencer DRAM parameters and control registers. Used for Self-Refresh
>  Power-Down (SRPD), among other things.
>  
>  Required properties:
> -- compatible     : should contain "brcm,brcmstb-memc-ddr"
> +- compatible     : should contain one of these
> +	"brcm,brcmstb-memc-ddr-rev-b.2.2"
> +	"brcm,brcmstb-memc-ddr"
>  - reg            : the MEMC DDR register range
>  
>  Example:
> -- 
> 2.9.3
> 

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