linux-kernel - Re: [PATCH] drm/i915: Pass enum pipe to intel_set_pch_fifo_underrun

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Date:   Thu, 20 Jul 2017 10:27:54 +0200
From:   Daniel Vetter <daniel@...ll.ch>
To:     Matthias Kaehlcke <mka@...omium.org>
Cc:     Daniel Vetter <daniel@...ll.ch>,
        Jani Nikula <jani.nikula@...ux.intel.com>,
        David Airlie <airlied@...ux.ie>,
        Daniel Vetter <daniel.vetter@...el.com>,
        intel-gfx <intel-gfx@...ts.freedesktop.org>,
        dri-devel@...ts.freedesktop.org,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Stéphane Marchesin 
        <stephane.marchesin@...il.com>,
        Grant Grundler <grundler@...omium.org>
Subject: Re: [PATCH] drm/i915: Pass enum pipe to
 intel_set_pch_fifo_underrun_reporting()

On Wed, Jul 19, 2017 at 10:39:28AM -0700, Matthias Kaehlcke wrote:
> Commit a21960339c8c ("drm/i915: Consistently use enum pipe for PCH
> transcoders") misses some pieces, due to a problem with the patch
> format, this patch adds the remaining bits.
> 
> Fixes: a21960339c8c ("drm/i915: Consistently use enum pipe for PCH
> transcoders")
> 
> Signed-off-by: Matthias Kaehlcke <mka@...omium.org>

Applied, and this time successfully it seems!

Thanks a lot, and sorry for the slight ordeal, I still have no clear idea
what happened with your v2 patch.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c | 12 ++++--------
>  1 file changed, 4 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a89d0fd1c2e1..5c7054c3be0e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5347,8 +5347,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  		return;
>  
>  	if (intel_crtc->config->has_pch_encoder)
> -		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
> -						      false);
> +		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
>  
>  	intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
>  
> @@ -5433,8 +5432,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  		intel_wait_for_vblank(dev_priv, pipe);
>  		intel_wait_for_vblank(dev_priv, pipe);
>  		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> -		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
> -						      true);
> +		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
>  	}
>  
>  	/* If we change the relative order between pipe/planes enabling, we need
> @@ -5531,8 +5529,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
>  	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
>  
>  	if (intel_crtc->config->has_pch_encoder)
> -		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
> -						      false);
> +		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
>  
>  	intel_encoders_disable(crtc, old_crtc_state, old_state);
>  
> @@ -5560,8 +5557,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
>  	intel_encoders_post_disable(crtc, old_crtc_state, old_state);
>  
>  	if (old_crtc_state->has_pch_encoder)
> -		intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
> -						      true);
> +		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
>  }
>  
>  static void i9xx_pfit_enable(struct intel_crtc *crtc)
> -- 
> 2.14.0.rc0.284.gd933b75aa4-goog
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch