linux-kernel - [PATCH] clk: Don't write error code into divider register

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 25 Jul 2017 13:18:40 +0300
From:   Peter De Schrijver <pdeschrijver@...dia.com>
To:     Peter De Schrijver <pdeschrijver@...dia.com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...eaurora.org>,
        <linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC:     Alex Frid <afrid@...dia.com>
Subject: [PATCH] clk: Don't write error code into divider register

From: Alex Frid <afrid@...dia.com>

Add a check for error returned by divider value calculation to avoid
writing error code into hw register.

Signed-off-by: Alex Frid <afrid@...dia.com>
Reviewed-by: Peter De Schrijver <pdeschrijver@...dia.com>
Reviewed-by: Jon Mayo <jmayo@...dia.com>
---
 drivers/clk/clk-divider.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 9bb472c..4ed516c 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -385,12 +385,14 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 				unsigned long parent_rate)
 {
 	struct clk_divider *divider = to_clk_divider(hw);
-	unsigned int value;
+	int value;
 	unsigned long flags = 0;
 	u32 val;
 
 	value = divider_get_val(rate, parent_rate, divider->table,
 				divider->width, divider->flags);
+	if (value < 0)
+		return value;
 
 	if (divider->lock)
 		spin_lock_irqsave(divider->lock, flags);
@@ -403,7 +405,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 		val = clk_readl(divider->reg);
 		val &= ~(div_mask(divider->width) << divider->shift);
 	}
-	val |= value << divider->shift;
+	val |= (u32)value << divider->shift;
 	clk_writel(val, divider->reg);
 
 	if (divider->lock)
-- 
1.9.1