linux-kernel - [PATCH] x86/idt: Fix the X86_TRAP

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Date:   Fri, 1 Sep 2017 10:26:30 +0200
From:   Ingo Molnar <mingo@...nel.org>
To:     Andrei Vagin <avagin@...tuozzo.com>
Cc:     tip-bot for Jacob Shin <tipbot@...or.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Cyrill Gorcunov <gorcunov@...nvz.org>,
        linux-tip-commits@...r.kernel.org, luto@...nel.org,
        peterz@...radead.org, rostedt@...dmis.org,
        linux-kernel@...r.kernel.org, hpa@...or.com, brgerst@...il.com,
        jpoimboe@...hat.com, bp@...en8.de, torvalds@...ux-foundation.org,
        dvlasenk@...hat.com
Subject: [PATCH] x86/idt: Fix the X86_TRAP_BP gate


Hi Andrei,

* Andrei Vagin <avagin@...tuozzo.com> wrote:

> Hi Thomas,
> 
> We run CRIU tests for linux-next and today they detected an issue. I've
> bisected this problem and it looks like a problem is in this patch.

Ok, there appears to be a bug in that conversion - does the patch below fix the 
regression for you?

Thanks,

	Ingo

================================>
Subject: x86/idt: Fix the X86_TRAP_BP gate
From: Ingo Molnar <mingo@...nel.org>

Andrei Vagin reported a CRIU regression and bisected it back to:

  90f6225fba0c ("x86/idt: Move IST stack based traps to table init")

This table init conversion loses the system-gate property of X86_TRAP_BP
and erroneously moves it from DPL3 to DPL0.

Fix it.

Reported-by: Andrei Vagin <avagin@...tuozzo.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
arch/x86/kernel/idt.c | 6 +++++-
 arch/x86/kernel/idt.c |    6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

Index: tip/arch/x86/kernel/idt.c
===================================================================
--- tip.orig/arch/x86/kernel/idt.c
+++ tip/arch/x86/kernel/idt.c
@@ -44,6 +44,10 @@ struct idt_data {
 #define ISTG(_vector, _addr, _ist)			\
 	G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS)
 
+/* System interrupt gate with interrupt stack */
+#define SISTG(_vector, _addr, _ist)			\
+	G(_vector, _addr, _ist, GATE_INTERRUPT, DPL3, __KERNEL_CS)
+
 /* Task gate */
 #define TSKG(_vector, _gdt)				\
 	G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
@@ -181,7 +185,7 @@ gate_desc debug_idt_table[IDT_ENTRIES] _
 static const __initdata struct idt_data ist_idts[] = {
 	ISTG(X86_TRAP_DB,	debug,		DEBUG_STACK),
 	ISTG(X86_TRAP_NMI,	nmi,		NMI_STACK),
-	ISTG(X86_TRAP_BP,	int3,		DEBUG_STACK),
+	SISTG(X86_TRAP_BP,	int3,		DEBUG_STACK),
 	ISTG(X86_TRAP_DF,	double_fault,	DOUBLEFAULT_STACK),
 #ifdef CONFIG_X86_MCE
 	ISTG(X86_TRAP_MC,	&machine_check,	MCE_STACK),