lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Fri, 1 Sep 2017 10:01:46 +0800 From: Elaine Zhang <zhangqing@...k-chips.com> To: mturquette@...libre.com, sboyd@...eaurora.org, heiko@...ech.de Cc: linux-clk@...r.kernel.org, linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, xxx@...k-chips.com, xf@...k-chips.com, huangtao@...k-chips.com, cl@...k-chips.com, Elaine Zhang <zhangqing@...k-chips.com> Subject: [PATCH v1 3/3] clk: rockchip: rk3126: add sclk_timer5 as critical clock sclk_timer5 is for arm arch counter, so need always on. but no dts node to handle this clk, so make it as critical clock Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com> --- drivers/clk/rockchip/clk-rk3128.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c index ce02d2cff608..5970a50671b9 100644 --- a/drivers/clk/rockchip/clk-rk3128.c +++ b/drivers/clk/rockchip/clk-rk3128.c @@ -578,6 +578,7 @@ enum rk3128_plls { "hclk_peri", "pclk_peri", "pclk_pmu", + "sclk_timer5", }; static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np) -- 1.9.1
Powered by blists - more mailing lists