linux-kernel - [PATCH 3/3] clk: hisilicon: correct ir clock rate for hi3798cv200 SoC

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Date:   Wed, 18 Oct 2017 07:00:29 -0400
From:   Jiancheng Xue <xuejiancheng@...ilicon.com>
To:     <sboyd@...eaurora.org>, <mturquette@...libre.com>
CC:     <linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <hermit.wangheming@...ilicon.com>, <shawn.guo@...aro.org>,
        <project-aspen-dev@...aro.org>,
        Younian Wang <wangyounian@...ilicon.com>
Subject: [PATCH 3/3] clk: hisilicon: correct ir clock rate for hi3798cv200 SoC

From: Younian Wang <wangyounian@...ilicon.com>

Correct ir clock rate for hi3798cv200 SoC.

Signed-off-by: Younian Wang <wangyounian@...ilicon.com>
---
 drivers/clk/hisilicon/crg-hi3798cv200.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c
index 25d750c..61bd941 100644
--- a/drivers/clk/hisilicon/crg-hi3798cv200.c
+++ b/drivers/clk/hisilicon/crg-hi3798cv200.c
@@ -258,7 +258,7 @@ static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
 #define HI3798CV200_SYSCTRL_NR_CLKS 16
 
 static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
-	{ HISTB_IR_CLK, "clk_ir", "100m",
+	{ HISTB_IR_CLK, "clk_ir", "24m",
 		CLK_SET_RATE_PARENT, 0x48, 4, 0, },
 	{ HISTB_TIMER01_CLK, "clk_timer01", "24m",
 		CLK_SET_RATE_PARENT, 0x48, 6, 0, },
-- 
2.7.4