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Date:   Fri, 10 Nov 2017 18:44:51 -0800
From:   Stephen Boyd <sboyd@...eaurora.org>
To:     Guodong Xu <guodong.xu@...aro.org>
Cc:     mturquette@...libre.com, chenjun14@...wei.com,
        zhongkaihua@...wei.com, zhangfei.gao@...aro.org,
        leo.yan@...aro.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH] clk: hi3660: fix incorrect uart3 clock freqency

On 08/07, Guodong Xu wrote:
> From: Zhong Kaihua <zhongkaihua@...wei.com>
> 
> UART3 clock rate is doubled in previous commit.
> 
> This error is not detected until recently a mezzanine board which makes
> real use of uart3 port (through LS connector of 96boards) was setup
> and tested on hi3660-hikey960 board.
> 
> This patch changes clock source rate of clk_factor_uart3 to 100000000.
> 
> Signed-off-by: Zhong Kaihua <zhongkaihua@...wei.com>
> Signed-off-by: Guodong Xu <guodong.xu@...aro.org>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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