lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Mon, 13 Nov 2017 21:25:15 +0100 (CET)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     "Dey, Megha" <megha.dey@...el.com>
cc:     Peter Zijlstra <peterz@...radead.org>,
        Megha Dey <megha.dey@...ux.intel.com>,
        "x86@...nel.org" <x86@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "hpa@...or.com" <hpa@...or.com>,
        "andriy.shevchenko@...ux.intel.com" 
        <andriy.shevchenko@...ux.intel.com>,
        "kstewart@...uxfoundation.org" <kstewart@...uxfoundation.org>,
        "Yu, Yu-cheng" <yu-cheng.yu@...el.com>,
        "Brown, Len" <len.brown@...el.com>,
        "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "acme@...nel.org" <acme@...nel.org>,
        "alexander.shishkin@...ux.intel.com" 
        <alexander.shishkin@...ux.intel.com>,
        "jolsa@...hat.com" <jolsa@...hat.com>,
        "namhyung@...nel.org" <namhyung@...nel.org>,
        "vikas.shivappa@...ux.intel.com" <vikas.shivappa@...ux.intel.com>,
        "pombredanne@...b.com" <pombredanne@...b.com>,
        "me@...ehuey.com" <me@...ehuey.com>, "bp@...e.de" <bp@...e.de>,
        "Andrejczuk, Grzegorz" <grzegorz.andrejczuk@...el.com>,
        "Luck, Tony" <tony.luck@...el.com>,
        "corbet@....net" <corbet@....net>,
        "Shankar, Ravi V" <ravi.v.shankar@...el.com>
Subject: RE: [PATCH V1 2/3] perf/x86/intel/bm.c: Add Intel Branch Monitoring
 support

On Mon, 13 Nov 2017, Dey, Megha wrote:
> >-----Original Message-----
> >From: Peter Zijlstra [mailto:peterz@...radead.org]
> >Sent: Monday, November 13, 2017 1:00 AM
> >To: Megha Dey <megha.dey@...ux.intel.com>
> >Cc: x86@...nel.org; linux-kernel@...r.kernel.org; linux-

Please fix your mail client so it does not add this complete useless
information to the reply.

> >On Sat, Nov 11, 2017 at 01:20:05PM -0800, Megha Dey wrote:
> >> +/*
> >> + * Unmask the NMI bit of the local APIC the first time task is
> >> +scheduled
> >> + * on a particular CPU.
> >> + */
> >> +static void intel_bm_unmask_nmi(void) {
> >> +	this_cpu_write(bm_unmask_apic, 0);
> >> +
> >> +	if (!(this_cpu_read(bm_unmask_apic))) {
> >> +		apic_write(APIC_LVTPC, APIC_DM_NMI);
> >> +		this_cpu_inc(bm_unmask_apic);
> >> +	}
> >> +}
> >
> >What? Why?
> 

> Normally, other drivers using perf create an event on every CPU (thereby
> calling perf_init on every CPU), where this bit(APIC_DM_NMI)is explicitly
> unmasked.  In our driver, we do not do this (since we are worried only
> about a particular task) and hence this bit is only disabled on the local
> APIC where the perf event is initialized.
>
> As such, if the task is scheduled out to some other CPU, this bit is set
> and hence would stop the interrupt from reaching the processing core.

Still that code makes no sense at all and certainly does not do what you
claim it does:

> >> +	this_cpu_write(bm_unmask_apic, 0);
> >> +
> >> +	if (!(this_cpu_read(bm_unmask_apic))) {

So first you write the per cpu variable to 0 and then you check whether it
is zero, which is pointless obviously.

> >
> >> +static int intel_bm_event_add(struct perf_event *event, int mode) {

Please move the opening bracket of the function into the next line. See the
kernel coding style documentation.

Thanks,

	tglx

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ