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Date: Thu, 7 Dec 2017 15:50:30 +0000 From: alexander.levin@...izon.com To: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "stable@...r.kernel.org" <stable@...r.kernel.org> Cc: Michał Mirosław <mirq-linux@...e.qmqm.pl>, "Thierry Reding" <treding@...dia.com>, alexander.levin@...izon.com Subject: [PATCH AUTOSEL for 4.4 074/101] clk: tegra: Fix cclk_lp divisor register From: Michał Mirosław <mirq-linux@...e.qmqm.pl> [ Upstream commit 54eff2264d3e9fd7e3987de1d7eba1d3581c631e ] According to comments in code and common sense, cclk_lp uses its own divisor, not cclk_g's. Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30") Signed-off-by: Michał Mirosław <mirq-linux@...e.qmqm.pl> Acked-By: Peter De Schrijver <pdeschrijver@...dia.com> Signed-off-by: Thierry Reding <treding@...dia.com> Signed-off-by: Sasha Levin <alexander.levin@...izon.com> --- drivers/clk/tegra/clk-tegra30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index b90db615c29e..8c41c6fcb9ee 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1063,7 +1063,7 @@ static void __init tegra30_super_clk_init(void) * U71 divider of cclk_lp. */ clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", - clk_base + SUPER_CCLKG_DIVIDER, 0, + clk_base + SUPER_CCLKLP_DIVIDER, 0, TEGRA_DIVIDER_INT, 16, 8, 1, NULL); clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL); -- 2.11.0
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