linux-kernel - [PATCH v2 15/34] clk: vc5: change vc5_dbl_round

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [day] [month] [year] [list]

Date:   Mon,  1 Jan 2018 19:34:41 +0000
From:   Bryan O'Donoghue <pure.logic@...us-software.ie>
To:     bryan.odonoghue@...us-software.ie
Cc:     Bryan O'Donoghue <pure.logic@...us-software.ie>,
        Marek Vasut <marek.vasut@...il.com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...eaurora.org>, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Vladimir Barinov <vladimir.barinov+renesas@...entembedded.com>,
        Alexey Firago <alexey_firago@...tor.com>
Subject: [PATCH v2 15/34] clk: vc5: change vc5_dbl_round_rate() return logic

This patch updates the round_rate() logic here to return zero instead of a
negative number on error.

In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.

Signed-off-by: Bryan O'Donoghue <pure.logic@...us-software.ie>
Cc: Marek Vasut <marek.vasut@...il.com>
Cc: Michael Turquette <mturquette@...libre.com>
Cc: Stephen Boyd <sboyd@...eaurora.org>
Cc: linux-clk@...r.kernel.org
Cc: linux-kernel@...r.kernel.org
Cc: Vladimir Barinov <vladimir.barinov+renesas@...entembedded.com>
Cc: Alexey Firago <alexey_firago@...tor.com>
---
 drivers/clk/clk-versaclock5.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
index 9432122..733b402 100644
--- a/drivers/clk/clk-versaclock5.c
+++ b/drivers/clk/clk-versaclock5.c
@@ -294,7 +294,7 @@ static unsigned long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,
 	if ((*parent_rate == rate) || ((*parent_rate * 2) == rate))
 		return rate;
 	else
-		return -EINVAL;
+		return 0;
 }
 
 static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,
-- 
2.7.4