linux-kernel - Re: [PATCH 3/7] x86/enter: Use IBRS on syscall and interrupts

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Date:   Thu, 4 Jan 2018 23:33:21 +0100
From:   Peter Zijlstra <peterz@...radead.org>
To:     Tim Chen <tim.c.chen@...ux.intel.com>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Andy Lutomirski <luto@...nel.org>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        Greg KH <gregkh@...uxfoundation.org>,
        Dave Hansen <dave.hansen@...el.com>,
        Andrea Arcangeli <aarcange@...hat.com>,
        Andi Kleen <ak@...ux.intel.com>,
        Arjan Van De Ven <arjan.van.de.ven@...el.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/7] x86/enter: Use IBRS on syscall and interrupts

On Thu, Jan 04, 2018 at 09:56:44AM -0800, Tim Chen wrote:
> Set IBRS upon kernel entrance via syscall and interrupts. Clear it
> upon exit.

So not only did we add a CR3 write, we're now adding an MSR write to the
entry/exit paths. Please tell me that these are 'fast' MSRs? Given
people are already reporting stupid numbers with just the existing
PTI/CR3, what kind of pain are we going to get from adding this?

> If NMI runs when exiting kernel between IBRS_DISABLE and
> SWAPGS, the NMI would have turned on IBRS bit 0 and then it would have
> left enabled when exiting the NMI. IBRS bit 0 would then be left
> enabled in userland until the next enter kernel.
> 
> That is a minor inefficiency only, but we can eliminate it by saving
> the MSR when entering the NMI in save_paranoid and restoring it when
> exiting the NMI.
> 
> Signed-off-by: Andrea Arcangeli <aarcange@...hat.com>
> Signed-off-by: Tim Chen <tim.c.chen@...ux.intel.com>

Invalid SoB chain, either you lost a From: Andrea or you need something
else.